View SAA6721_238806.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

INTEGRATED CIRCUITS
DATA SHEET
SAA6721E SXGA RGB to TFT graphics engine
Preliminary specification File under Integrated Circuits, IC02 1999 May 11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
CONTENTS 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 2 3 4 5 6 7 7.1 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 7.4 7.5 7.5.1 7.5.2 7.6 7.6.1 7.6.2 7.7 7.8 7.8.1 7.8.2 7.8.3 7.9 7.9.1 7.9.2 8 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 FEATURES RGB video input YUV video input Video processing On screen display Video output Memory interface Miscellaneous GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION Data path System clocks Input interface clock (VCLK) Memory interface clock (MCLKI) I2C-bus interface clock (SCL) System clock (CLK) TFT panel clock (PCLK) RGB input port YUV input port TFT output port Single pixel mode Double pixel mode Memory port SDRAM memory configuration SGRAM memory configuration I2C-bus interface De-interlacing algorithms Static mesh mode Spatial filtering Temporal filtering Scaling algorithm Upscaling Downscaling SYSTEM DESCRIPTION Programming registers Clock management Clock generation and multiplexing Clock divider RGB/YUV input interface Sampling mode RGB data sampling Clamp pulse generation Gain correction pulse generation YUV data sampling 2 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 8.6 8.6.1 8.6.2 8.6.3 8.7 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.9 8.10 8.11 8.11.1 8.11.2 8.11.3 8.12 8.13 8.13.1 8.13.2 8.13.3 9 10 11 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17
SAA6721E
Video mode and synchronization signal detection Memory interface and de-interlacer unit Memory interface limitations Initialization of external memory Frame and field memory Frame recovery Scaling Downscaling Upscaling Upscaler transition function Panning unit Overlay port Overlay insertion Sync generation Data sampling OVCLK gating Colour space matrix Colour correction On screen display OSD generals OSD window OSD character matrix Temporal dithering (frame rate controller) Output interface General Frame generation Timing reference signals LIMITING VALUES CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1999 May 11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
1 1.1 FEATURES RGB video input
SAA6721E
* Digital single (24-bit) or dual (48-bit) channel RGB input * Data input of sampled RGB data with a pixel frequency of maximum 150 MHz * Free definable data acquisition offsets and vertical window size in single pixel increments, horizontal window size in double pixel increments * Programmable pulses for ADC clamping and ADC gain correction * Detection of presence of sync signals, and of their polarities * Support for auto-adjustment functions for sample clock frequency, phase, vertical and horizontal sample offset, as well as colour adjustment * Maximum supported resolution of 1280 x 1024 dots Super Extended Graphics Adapter (SXGA) * Support for detection of the applied graphics mode (multi-sync). 1.2 YUV video input 1.4 On screen display * Character based internal On Screen Display (OSD) * Programmable character matrix sizes of either 24 x 24 pixels (42 characters available) or 12 x 16 pixels (128 characters available) * Programmable width and height of the OSD window, built from maximum 1152 characters * 8 different colours for foreground and background inclusive transparent colours * Overlay port for external OSD controller. 1.5 Video output
* Single pixel/clock (24-bit) or double pixel/clock (48-bit) digital RGB output * Generation of synchronization and validation signals for the Thin Film Transistor (TFT) display * Frame rate control (temporal dithering) for displaying true colour graphics on high colour displays * Free programmable timing for displays of several manufacturers. 1.6 Memory interface
* Pin sharing between YUV and RGB input port * YUV 4 : 4 : 4, YUV 4 : 2 : 2, YUV 4 : 2 : 2 with CCIR 656 codes, YUV 4 : 1 : 1 input of interlaced and non-interlaced digital video data * Maximum picture resolution of 1024 x 1024 pixels for interlaced or non-interlaced video * Input of video data at maximum 75 MHz * Free definable data acquisition offsets and window in double pixel or single line increments * YUV to RGB colour space conversion. 1.3 Video processing
* Support of both 1M x 16 SDRAM, 256k x 32 SGRAM or 128k x 32 SGRAM devices * Maximum memory clock frequency of 125 MHz * Scalable memory size built of either 2, 3 or 4 SDRAM, or of 1 or 2 SGRAM devices * Special mode for operation without external memory. 1.7 Miscellaneous
* Colour correction Look-Up Table (LUT) * Phase correct up and downscaling of the RGB data * Fully programmable scaling ratios * Independent horizontal and vertical scaling engine * Free definable position of the scaled input picture inside the output picture with programmable border colour * De-interlacing unit for digital YUV video data * Zoom up to full-screen resolution of the de-interlaced YUV video stream via the main scaler.
* Internal Phase-Locked Loop (PLL) for memory and panel clock generation from the system clock * I2C-bus interface with 2 selectable addresses * Boundary scan test circuit and Joint Test Action Group (JTAG) test controller.
1999 May 11
3
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
2 GENERAL DESCRIPTION
SAA6721E
The SAA6721E must be embedded into a system containing a microcontroller with an I2C-bus serial interface. For multi-sync capabilities a frame buffer built from SGRAM or SDRAM is needed. The size of this frame buffer depends on the maximum resolution and bandwidth needed for the application. For converting the analog RGB stream into a digital data stream one or two ADCs with 3 channels each for R, G and B are needed. If the YUV input is used, a video front-end chip such as the SAA7113 must be used in front of the YUV port.
The SAA6721E is a graphics engine, which converts digital RGB or YUV data into video signals suitable for TFT displays. It supports SXGA input resolution as well as true colour. Independent horizontal and vertical up and downscaling can display the input data arbitrarily on the connected TFT display. Multi-sync capability allows the applied graphics mode to be detected. Overlay signals can be generated either by an internal OSD generator or supplied via the overlay port from an external OSD controller. 3 QUICK REFERENCE DATA SYMBOL VDDD IDDD Vi Vo Tamb 4 PARAMETER digital supply voltage digital supply current input voltages output voltages memory port output voltages TFT port ambient temperature
MIN. 3.0 - 3.3 600
TYP. 3.6
MAX. V mA 840
UNIT
LVTTL compatible LVTTL compatible CMOS compatible 0 - 70 C
ORDERING INFORMATION PACKAGE TYPE NUMBER NAME DESCRIPTION plastic ball grid array package; 292 balls; body 27 x 27 x 1.75 mm VERSION SOT489-1
SAA6721E
BGA292
1999 May 11
4
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
handbook, full pagewidth
1999 May 11
SCL MODE/SYNC DETECTION input frame size and sync information frequency, phase and colour information AUTO ADJUSTMENT CONTROLLER VCLK VVS VHS CLAMP GAINC VPA7 to VPA0 VPB7 to VPB0 VPC7 to VPC0 VPD7 to VPD0 VPE7 to VPE0 VPF7 to VPF0 RGB/YUV data RGB/YUV INPUT INTERFACE YUV RGB RGB raw data LINE MEMORY
5
Philips Semiconductors
SXGA RGB to TFT graphics engine
BLOCK DIAGRAM
OVA2 to OVA0 OVVS INT RST TDO TDI TMS TCLK OVACT TRST OVB2 to OVB0 OVHS OVCLK
SDA
SAD
I2C-BUS INTERFACE
GLOBAL CONTROL UNIT
JTAG CONTROLLER
UP SCALER
COLOUR CORRECTION
PANNING UNIT
OSD OVERLAY PORT
5
SAA6721E
ON SCREEN DISPLAY
TEMPORAL DITHERING
PAR7 to PAR0 PAG7 to PAG0 PAB7 to PAB0 PBR7 to PBR0
DOWN SCALER
MEMORY INTERFACE
OUTPUT INTERFACE
PBG7 to PBG0 PBB7 to PBB0 PVS PHS PDE
MCLKI
/2
CLK PLL DIVIDER
memory clock panel clock
DE-INTERLACER
PCLK
Preliminary specification
MHB241
SAA6721E
DQ63 DQM to DQ0
BA
A10 to A0
RAS
CAS
WE MCLKO
VSSD
VDDD
VDD(PLL) VSS(PLL)
Fig.1 Block diagram.
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
6 PINNING INFORMATION
SAA6721E
MHB242
handbook, halfpage
Y V
W U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7
SAA6721E
8
9
10 12 14 16 18 20 11 13 15 17 19
Fig.2 Pin configuration.
Table 1 SYMBOL VCLK VVS VHS VPA7 VPA6 VPA5 VPA4 VPA3 VPA2 VPA1 VPA0 PIN N1 M3 M2 C7 A6 B6 C6 A5 D5 B5 C5 PORT RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input I/O(1) input input input input input input input input input input input DESCRIPTION RGB/YUV sample clock RGB/YUV vertical sync RGB/YUV horizontal sync video input port A; RGB port 0 red channel or YUV port luminance
1999 May 11
6
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL VPB7 VPB6 VPB5 VPB4 VPB3 VPB2 VPB1 VPB0 VPC7 VPC6 VPC5 VPC4 VPC3 VPC2 VPC1 VPC0 VPD7 VPD6 VPD5 VPD4 VPD3 VPD2 VPD1 VPD0 VPE7 VPE6 VPE5 VPE4 VPE3 VPE2 VPE1 VPE0 VPF7 VPF6 VPF5 VPF4 VPF3 VPF2 VPF1 VPF0
PIN A4 B4 C4 A3 B3 C3 A2 B2 B1 C2 C1 D3 D2 D1 E3 E2 E4 E1 F3 F2 F1 G3 G2 G4 G1 H3 H2 H1 J2 J4 J1 K3 K2 K1 L1 L4 L2 L3 M1 M4
PORT RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input RGB/YUV input
I/O(1) input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input input
DESCRIPTION video input port B; RGB port 0 green channel or YUV port chrominance
video input port C; RGB port 0 blue channel or YUV port chrominance
video input port D; RGB port 1 red channel or YUV data qualifier port (VPD7 = CREF clock gating signal; VPD6 = HREF active horizontal video)
video input port E; RGB port 1 green channel
video input port F; RGB port 1 blue channel
1999 May 11
7
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL CLAMP GAINC PCLK PVS PHS PDE PAR7 PAR6 PAR5 PAR4 PAR3 PAR2 PAR1 PAR0 PAG7 PAG6 PAG5 PAG4 PAG3 PAG2 PAG1 PAG0 PAB7 PAB6 PAB5 PAB4 PAB3 PAB2 PAB1 PAB0 PBR7 PBR6 PBR5 PBR4 PBR3 PBR2 PBR1 PBR0
PIN N2 N3 Y13 V12 U12 P1 P4 P2 P3 R1 R2 R3 T1 T4 T2 T3 U1 U2 V1 V2 W1 Y1 W2 Y2 V3 W3 Y3 V4 Y4 V5 W5 Y5 V6 W6 Y6 V7 W7
PORT RGB/YUV input RGB/YUV input panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface
I/O(1) output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output
DESCRIPTION clamp pulse for analog-to-digital converter gain correction pulse for analog-to-digital converter panel clock panel vertical sync panel horizontal sync panel data enable panel port A red channel
W12 panel interface
panel port A green channel
panel port A blue channel
panel port B red channel
1999 May 11
8
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL PBG7 PBG6 PBG5 PBG4 PBG3 PBG2 PBG1 PBG0 PBB7 PBB6 PBB5 PBB4 PBB3 PBB2 PBB1 PBB0 SCL SDA SAD OVCLK OVVS OVHS OVACT OVA0 OVA1 OVA2 OVB0 OVB1 OVB2 MCLKO RAS CAS WE DQM
PIN Y7 V8 W8 Y8 V9 W9 U9 Y9 V10 Y10 Y11 U11 V11 Y12 V18 W18 Y17 Y16 V15 V16 Y14 V13 Y15 V14 A17 A18 C17 D16 T17 overlay overlay overlay overlay overlay overlay overlay W16 overlay
PORT panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface panel interface I2C-bus interface
I/O(1) output output output output output output output output output output output output output output output output input input/output input output output output input input input input input input input output output output output output
DESCRIPTION panel port B green channel
panel port B blue channel
W10 panel interface
W11 panel interface
I2C-bus interface clock line I2C-bus interface data line I2C-bus address select: 0 = 74H, 1 = 76H overlay port clock overlay port vertical sync overlay port horizontal sync overlay port pixel active overlay port input pixel A
W13 overlay
overlay port input pixel B
W14 overlay memory interface memory interface memory interface memory interface memory interface
memory clock output memory Row Address Strobe (RAS) signal (active LOW) memory Column Address Strobe (CAS) signal (active LOW) memory Write Enable (WE) signal (active LOW) memory data mask (active LOW)
1999 May 11
9
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 1999 May 11
PIN A20 C20 D20 E19 F18 E17 E18 C19 C18 D18 B19 A19
PORT memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface
I/O(1) output output output output output output output output output output output output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output 10 memory bank select memory data bus
DESCRIPTION memory address bus
M20 memory interface M19 memory interface N20 N19 P19 R19 T20 T19 T18 R18 P18 P17 N18 memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface
M18 memory interface M17 memory interface L19 E20 F20 H20 J20 K19 K20 L20 K17 K18 J19 J18 H19 memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface
G20 memory interface
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 TCLK TRST TDI TMS TDO
PIN H18 F19 A12 B12 A13 B13 A14 B14 A15 B15 A16 C15 C14 D14 C13 C12 D12 C11 B7 A7 B8 A8 B9 A9 B10 A10 B11 A11 D10 C10 D9 C9 C8 D7 U19 W17 U18 V19 W19
PORT memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface memory interface JTAG test controller
I/O(1) input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input/output input input input input output memory data bus
DESCRIPTION
G18 memory interface
JTAG test controller clock; note 2 JTAG test controller reset (active LOW); note 2 JTAG test data input; note 2 JTAG test mode select; note 2 JTAG test data output
1999 May 11
11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL CLK RST INT MCLKI VSSD
PIN Y19 Y20 Y18 W20 A1 D4 D8 D13 D17 H4 H17 N4 N17 U4 U8 U13 U17 -
PORT miscellaneous
I/O(1) input input output input -
DESCRIPTION system and panel clock system reset (active LOW) mode detection interrupt (active LOW) memory clock input digital ground supply
VDDD
D6 D11 D15 F4 F17 K4 L17 R4 R17 U6 U10 U15
-
-
digital supply voltage
VSS(PLL) VDD(PLL) n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. 1999 May 11
V17 U16 B16 B17 B18 B20 C16 D19
- - - - - - - -
- - - - - - - - - - - - 12
ground supply for internal PLL circuitry supply voltage for internal PLL circuitry not connected not connected not connected not connected not connected not connected not connected not connected not connected not connected
G17 - G19 - J3 J17 - -
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. Notes
PIN L18 P20 R20 U3 U5 U7 U14 U20 V20 W4 - - - - - - - - - -
PORT - - - - - - - - - - -
I/O(1) not connected not connected not connected not connected not connected not connected not connected not connected not connected not connected not connected
DESCRIPTION
W15 -
1. Generally all inputs are 5 V tolerant TTL inputs. All outputs are CMOS, except the memory interface ports, which are LVTTL compatible. 2. Connect to ground when not using the JTAG controller. 7 7.1 FUNCTIONAL DESCRIPTION Data path 7.2 7.2.1 System clocks INPUT INTERFACE CLOCK (VCLK)
Input video data is sampled either as RGB data in single pixels from only one ADC or in double pixels in interleaved format from two ADCs. Alternatively the input interface can sample interlaced or non-interlaced YUV data. The clock for sampling the data will always be provided from external circuitry. The video stream will be adapted from the input frame rate to the output frame rate needed by the panel. Therefore a frame buffer built of SDRAMs or SGRAMs is used. If the panel supports the incoming frame rate from the RGB port, the adaption can be done without external memory. If the video stream is in interlaced format the memory interface activates its de-interlacing unit. If zooming must be performed the upscaler behind the memory interface will be enabled. For downscaling the downscaler in front of the memory interface in the data path will be used. A colour correction can be done via a look-up table. The resulting video stream can now be positioned elsewhere in the output data stream by the panning unit. If an external OSD controller is embedded into the system, its OSD window will be put into the video stream by the OSD overlay port. Additionally the internal OSD will be inserted in the next stage. The temporal dithering allows true colour pictures to be displayed on high colour panels. The output interface provides the timing and control signals necessary for the connected panel.
This clock is used for sampling the incoming RGB or YUV data stream. In RGB mode this clock varies from 25 to 150 MHz in single ADC mode. If two ADCs are used the RGB input clock is between 12.5 and 75 MHz. In YUV mode the clock lies in the range of approximately 30 MHz. The clocks are generated from external devices. The RGB clock can be generated by the external ADCs or an external video PLL. The YUV clock must be generated by the video decoder which also provides the YUV video data. 7.2.2 MEMORY INTERFACE CLOCK (MCLKI)
The memory clock is the synchronous clock for the external frame buffer. Depending on the bandwidth needed by the application, and the connected SDRAM or SGRAM devices, the clock varies from 83 to 125 MHz. It can be generated internally by the PLL from the system clock (CLK), or by an external quartz oscillator. If the internal PLL is used, the memory clock frequency can be derived from the following formula: f_system f_memory = ----------------------- x 16 N Where N = pre-divider ratio and f_system = clock at pin CLK.
1999 May 11
13
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
7.2.3 I2C-BUS INTERFACE CLOCK (SCL)
SAA6721E
Therefore ports VPD7 to VPD0, VPE7 to VPE0, and VPF7 to VPF0 are also needed. The VPA/B/C ports are sampled on the rising edge of the RGB input clock (VCLK), and the VPD/E/F ports on the falling edge (see Fig.3). The synchronization pulses from the graphics card are used to identify the frame outline. The vertical synchronization pulse is connected to pin VVS, and the horizontal synchronization pulse is connected to pin VHS. For calibrating the connected Analog-to-Digital Converter (ADC) the SAA6721E delivers a clamp pulse at pin CLAMP, and a gain correction pulse at pin GAINC (see Fig.4). The sample window of the RGB input port is controlled by four counters; horizontal and vertical offset, and horizontal and vertical window size. The offset counters start at the inactive or second edge of their corresponding synchronization signal.
This clock drives the interface to the external microcontroller. Its frequency range is from 100 kHz to 1 MHz. 7.2.4 SYSTEM CLOCK (CLK)
This clock is used to drive the internal PLL. The frequency range is from 24 to 50 MHz. 7.2.5 TFT PANEL CLOCK (PCLK)
This clock is the timing reference for the panel. The frequency is the same as the system clock, or it can be generated from the internal PLL by using the following formula: f_system 32 f_tft = ----------------------- x ----N M Where N = pre-divider ratio and M = post-divider ratio. 7.3 RGB input port
The RGB input port can operate in two modes; single pixel mode (24 bits) and double pixel mode (48 bits). For single pixel mode only ports VPA7 to VPA0, VPB7 to VPB0, and VPC7 to VPC0 are internally sampled. For double pixel mode two pixels must be provided at the RGB input port.
handbook, full pagewidth
VCLK
VPA/B/C
VPD/E/F
MHB243
Fig.3 RGB input port timing.
1999 May 11
14
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
handbook, full pagewidth
VHS
RGB data
blanking
GAINC
CLAMP
MHB244
Fig.4 Clamp and gain correction pulses.
7.4
YUV input port
The YUV input port supports interlaced video streams and provides an easy connection to most common decoder ICs. It consists of the luminance port VPA7 to VPA0, the chrominance port VPB7 to VPB0, and eventually VPC7 to VPC0, which are CCIR 601 level compatible (Y: 16 to 235, and UV: 16 to 240). Supported at this port are the formats YUV 4 : 1 : 1, YUV 4 : 2 : 2 and YUV 4 : 2 : 2 with CCIR 656 codes (see Table 2).
YUV 4 : 4 : 4 data can be applied at VPA7 to VPA0 (Y), VPB7 to VPB0 (U), and VPC7 to VPC0 (V). Input data is sampled with respect to the clock at pin VCLK if pin VPD7 (CREF) is asserted. The start of active video data in a line is marked by the rising edge at pin VPD6 (HREF) and the end of valid video data is marked by the falling edge at pin VPD6. Figure 5 illustrates this at a YUV 4 : 2 : 2 example.
handbook, full pagewidth
VCLK
CREF
HREF
Y7 to Y0
XX
Y0
Y1
Y2
Y3
...
Y5
Y6
Y719
XX
UV7 to UV0 XX
U0
V0
U2
V2
...
V716
U718
V718
XX
MHB245
Fig.5 CREF and HREF timing.
1999 May 11
15
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
Table 2 YUV input formats 4 : 1 : 1 FORMAT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 V07 V06 X X X X Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 U05 U04 V05 V04 X X X X
1 2VCLK
SAA6721E
SIGNAL Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 Data frequency
4 : 2 : 2 FORMAT Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 U01 U00 V01 V00 X X X X Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 U07 U06 U05 U04 U03 U02 U01 U00
1
CCIR 656 U07 U06 U05 U04 U03 U02 U01 U00 X X X X X X X X Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 X X X X X X X X VCLK V07 V06 V05 V04 V03 V02 V01 V00 X X X X X X X X Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 X X X X X X X X
Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 U03 U02 V03 V02 X X X X
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 V07 V06 V05 V04 V03 V02 V01 V00
2VCLK
For YUV 4 : 4 : 4 the Y, U, and V components are available in parallel. If non-interlaced video data is applied, it is treated as odd fields. Interlaced video data is sampled odd field, even field, odd field, even field, etc. If there are equal subsequent frames, only the first of these frames will be
sampled. The decoding of odd and even fields is done with HREF. In CCIR 656 data streams the included codes are used for identifying even and odd frames, blanking and active video data. The codes start with the byte sequence FF 00 00, followed by the reference code byte; see Figs 6 and 7.
handbook, full pagewidth
VCLK
Y7 to Y0 XX
FF
00
00
SAV
U0
Y0
V0
Y1
...
MHB246
Fig.6 CCIR 656 SAV code.
handbook, full pagewidth
VCLK
Y7 to Y0
...
U718
Y718
V718
Y719
FF
00
00
EAV
XX
MHB247
Fig.7 CCIR 656 EAV code.
1999 May 11
16
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
The CCIR 656 code byte contains vertical and horizontal blanking as well as odd and even field information, the protection bits P3 to P0 are ignored. Table 3 MSB 7 1 Notes 1. F = 0: odd field (field 1); F = 1: even field (field 2). 2. V = 0: in active field lines; V = 1: in field blanking. 3. H = 0: SAV (Start of Active Video); H = 1: EAV (End of Active Video). The sample window of the YUV input port is controlled by four counters; horizontal and vertical offset, and horizontal and vertical window size. The vertical offset counter starts counting from the inactive or second edge of its corresponding reference signal. The horizontal offset counter starts with the active edge of the HREF signal. 7.5 TFT output port 6 F(1) 5 V(2) 4 H(3) 3 P3 2 P2 1 P1 CCIR 656 code byte LSB 0 P0 7.5.2 DOUBLE PIXEL MODE
SAA6721E
The double pixel mode is used for direct connection of TFT panels with double pixel input. Both output ports are used. The first pixel is applied at port A, and the second at port B. 7.6 Memory port
The memory port connects the SAA6721E to the external frame buffer. This frame memory can be built from either 1M x 16 SDRAM or 256k x 32 SGRAM devices. Supported are RAM devices with clock frequencies up to 125 MHz. This clock can be provided either by the internal PLL, or externally be applied to pin MCLKI. The memory data bus is split into 4 ports: port 0 (DQ0 to DQ15), port 1 (DQ16 to DQ31), port 2 (DQ32 to DQ47) and port 3 (DQ48 to DQ63). To adapt the external memory to the needs of the application by means of memory size and bandwidth, it is possible to scale the external memory by using only the number of subsequent ports needed to build up the frame buffer and to achieve the memory bandwidth. As a second step for bandwidth optimization several speed grades of memory devices can be used. 7.6.1 SDRAM MEMORY CONFIGURATION
The TFT output port consists of two pixel ports (A and B), each containing red, green and blue colour information with a resolution of 8 bits per colour. The first pixel port is mapped to PAR7 to PAR0, PAG7 to PAG0, and PAB7 to PAB0. The second port is mapped to PBR7 to PBR0, PBG7 to PBG0, and PBB7 to PBB0. The vertical and horizontal synchronization signals are mapped to pins PVS and PHS. A data validation signal framing visible pixels is available at pin PDE. All of the above mentioned signals are synchronized to the output clock at pin PCLK. The active edge of this clock is programmable. 7.5.1 SINGLE PIXEL MODE
SDRAMs are available in sizes from 16 Mbits. For this application a wide data bus is required, so that at least 1M x 16 devices must be used. To achieve the desired bandwidth, 2 to 4 devices must be used in parallel, which results in a frame buffer size of 4 to 8 Mbytes. But only half of this memory will be used by the SAA6721E. The memory port of the SAA6721E can be divided into 4 SDRAM channels. Each channel is 16 bits wide, and provides in High Speed Channel (HSC) mode with a 125 MHz memory clock and an effective bandwidth of 228 Mbits/s. A Medium Speed Channel (MSC) with a 100 MHz memory clock gives an effective bandwidth of 182 Mbits/s, 91% effective bandwidth assumed. Table 4 gives the channel configuration for several input and panel resolutions.
The single pixel mode is designed to support TFT panels with single pixel input, and for direct connection of panel link transmitters. Only the first pixel port PAR7 to PAR0, PAG7 to PAG0, and PAB7 to PAB0 is used. The data is applied at double the frequency in comparison to the double pixel output mode.
1999 May 11
17
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
Table 4 SDRAM channel configurations SVGA (800 x 600) 60 Hz 288 Mbits/s bandwidth; 2 x HSC or 2 x MSC 307 Mbits/s bandwidth; 2 x HSC or 2 x MSC 75 Hz 319 Mbits/s bandwidth; 2 x HSC or 2 x MSC 337 Mbits/s bandwidth; 2 x HSC or 2 x MSC XGA (1024 x 768) 60 Hz 411 Mbits/s bandwidth; 2 x HSC or 3 x MSC 435 Mbits/s bandwidth; 2 x HSC or 3 x MSC 75 Hz 452 Mbits/s bandwidth; 2 x HSC or 3 x MSC 476 Mbits/s bandwidth; 3 x HSC or 3 x MSC
SAA6721E
INPUT RESOLUTION Panel XGA(1)
SXGA (1280 x 1024) 60 Hz 475 Mbits/s bandwidth; 3 x HSC or 3 x MSC 624 Mbits/s bandwidth; 3 x HSC or 4 x MSC 75 Hz 540 Mbits/s bandwidth; 3 x HSC or 3 x MSC 705 Mbits/s bandwidth; 4 x HSC or 4 x MSC
2 Mbits frame buffer needed
3 Mbits frame buffer needed
4 Mbits frame buffer needed
SXGA(2)
Notes 1. 36 MHz clock frequency. 2. 50 MHz clock frequency. 7.6.2 SGRAM MEMORY CONFIGURATION Each channel gives, in HSC mode with 125 MHz clock frequency, an effective bandwidth of 456 Mbits/s; and in MSC mode, with 100 MHz clock speed, an effective bandwidth of 364 Mbits/s. Table 5 gives the channel configuration for several input and panel resolutions.
SGRAM devices organized to 256k x 32 bits are available, and feature the wide data bus for high speed applications. With these devices a frame buffer can be built, without wasting memory because of bandwidth. In case of SGRAM usage, the memory data bus of the SAA6721E can be split into 2 channels of 32 bits each. Table 5 SGRAM channel configurations SVGA (800 x 600) 60 Hz 288 Mbits/s bandwidth; 1 x HSC or 1 x MSC 307 Mbits/s bandwidth; 1 x HSC or 1 x MSC 75 Hz 319 Mbits/s bandwidth; 1 x HSC or 1 x MSC 337 Mbits/s bandwidth; 1 x HSC or 1 x MSC
INPUT RESOLUTION Panel XGA(1)
XGA (1024 x 768) 60 Hz 411 Mbits/s bandwidth; 1 x HSC or 2 x MSC 435 Mbits/s bandwidth; 1 x HSC or 2 x MSC 75 Hz 452 Mbits/s bandwidth; 1 x HSC or 2 x MSC 476 Mbits/s bandwidth; 2 x HSC or 2 x MSC
SXGA (1280 x 1024) 60 Hz 475 Mbits/s bandwidth; 2 x HSC or 2 x MSC 624 Mbits/s bandwidth; 2 x HSC or 2 x MSC 75 Hz 540 Mbits/s bandwidth; 2 x HSC or 2 x MSC 705 Mbits/s bandwidth; 2 x HSC or 2 x MSC
2 Mbits frame buffer needed
3 Mbits frame buffer needed
4 Mbits frame buffer needed
SXGA(2)
Notes 1. 36 MHz clock frequency. 2. 50 MHz clock frequency.
1999 May 11
18
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
7.7 I2C-bus interface
SAA6721E
The device address of the SAA6721E must then be sent with the desired I/O direction. If the SAA6721E reads its device address, it acknowledges this by sending a single bit ACK to the master. If write mode was selected, the master sends the register address to be written and then the data bytes. If read mode was selected, the SAA6721E sends the data bytes starting from the last address accessed either by write command or the next address at a read command. All byte transfers are acknowledged from the receiving device. The data transfer is aborted by sending a STOP condition, when SDA changes from LOW to HIGH when SCL is HIGH (see Fig.9). If a new address has to be read or written, it is possible to send a new START condition without a preceding STOP condition. In this case the bus is still occupied by the master, and it can initiate a new data transfer. This is useful for read activities, where at first the register address must be sent in write mode and after that a read command will be sent to read data from this and following addresses.
This serial interface consists of only two signals, the serial clock line (SCL) and the serial data line (SDA). The maximum supported frequency on this bus is 1 MHz. Spikes with a maximum pulse length of 50 ns are suppressed by the internal input filter. The SAA6721E operates as a slave and cannot initiate any data transfer, so the clock line is always input. Via the data line, data is transmitted and received, so this pin must be input/output. The SCL and SDA lines are driven by open-drain stages and pull-up resistors. When a logic 0 is applied, the bus is set to ground level via the output buffers. When a logic 1 is applied, the output buffer switches to 3-state and the pull-up resistors pull the bus up to +5 V. Data transfer changes on SDA are allowed only when SCL is LOW. Data is sampled on the positive edge of SCL. In Idle state the output buffers are in 3-state, and the bus is HIGH. A data transfer must be initiated by an I2C-bus master device. This is done by sending a START condition when SDA changes from HIGH to LOW when SCL is HIGH (see Fig.8).
handbook,SCL full pagewidth
SDA
A6
A5
A4
A3
A2
A1
A0
R/W
ACK
R7
R6
R5
MHB248
START condition
acknowledge
Fig.8 Start of a data transfer.
handbook, full pagewidth SCL
SDA
D1
D0
ACK
D7
D6
D5
D4
D3
D2
D1
D0
A/A
acknowledge/ not acknowledge
STOP condition
MHB249
Fig.9 End of a data transfer.
1999 May 11
19
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
If the data transfer was a read transfer and the master was receiver, the master must not generate an acknowledge before the STOP condition. 7.8 De-interlacing algorithms 7.9 Scaling algorithm
SAA6721E
The missing even line in an odd frame will be calculated by interpolation from the corresponding even lines in the even fields before and after. The odd line handling is done in the same way.
The SAA6721E features several de-interlacing algorithms for processing interlaced video data. Depending on the algorithm different memory bandwidths and field memories are needed. 7.8.1 STATIC MESH MODE
The SAA6721E features different scaling engines for up and downscaling, for both horizontal and vertical processing. The horizontal scaling engines are independent from each other. The vertical scaling engines share the line buffer, so they cannot operate in parallel. 7.9.1 UPSCALING
This mode allows de-interlacing without any image processing and filtering. A field store for 2 fields is necessary. De-interlacing is achieved by simply putting lines together in the right order from the odd and even fields in the field store and generating the output frame. 7.8.2 SPATIAL FILTERING
The upscaling engine is used for enlarging the incoming video frames. It can be used for zooming both RGB and YUV video data. The magnification can be programmed individually for horizontal and vertical scaling. The maximum scaling factor for both directions is 64. The implemented filter algorithm (see Fig.10) uses interpolation with pixel enhancement, based on a free programmable transition function. It is therefore possible to define the transition between two calculated pixels to obtain different sharpness characteristics. This transition function must be defined in the 7 bits x 64 look-up table, with a number ranging from 0 to 64. Different functions can be programmed for horizontal and vertical scaling.
The spatial filtering mode requires 2 field memories, but only one memory is used at a time. For the calculation of the whole frame from an odd field, the missing even lines are interpolated from the odd lines before and after. Processing of the even field is done in the same way. 7.8.3 TEMPORAL FILTERING
The filtering algorithm needs 4 field memories and will be applied temporally to subsequent fields.
handbook, full pagewidth
intensity of output pixel O 100% A, 0% B
(3)
MHB250
A
B
(2)
O 0% A, 100% B 100% A, 0% B
(1)
0% A, 100% B
ratio between input pixels A, B
(1) The linear interpolation results in smoothing the sharp edges of the original picture if a pixel must be calculated. (2) Some kind of 1x function results in sharper edges, because of the smaller transition interval. (3) Phase correct pixel repetition can be done with this function.
Fig.10 Interpolation function definition.
1999 May 11
20
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
7.9.2 DOWNSCALING
SAA6721E
After writing to all registers the internal reset can be released. There are some registers (mainly offset counters) that can be changed during data processing without an internal reset. All accesses to the on screen display can be done during data processing. Table 6 MSB I2C-bus device address LSB 1 1 1 0 1 SAD R/W
The downscaling engine is used for reducing the incoming RGB data stream, i.e. for displaying high resolution input frames on panels with a smaller resolution. The scaling ratio can be programmed independently for both horizontal and vertical downscaling units. The algorithm uses pixel accumulation, achieving a minimum scaling factor of 164. 8 8.1 SYSTEM DESCRIPTION Programming registers
0
The SAA6721E is a highly integrated device with many features. To get the desired functionality and performance it must be programmed correctly. In general, before programming, the device must be switched to the internal reset state to prevent unwanted functions while changing the registers. Table 7 Programming register overview D7 D6 D5
Bit SAD = 0 the address is 74H, while bit SAD = 1 the address is 76H. Table 7 shows the programming model.
ADDRESS R/W State 0 1 2 3 R R R
D4
D3
D2
D1
D0
reserved reserved intr
R/W iic_test_register[7 to 0]
RGB mode detection 4 5 6 7 8 R R R R R h_clocks[7 to 0] h_clocks[11 to 8] v_lines[7 to 0] v_lines[10 to 8] pos_ vsync pos_ hsync no_ vsync no_ hsync
RGB auto-adjustment 9 10 11 12 13 14 15 16 17 18 W W W W W R R R R R ref_colour[7 to 0] ref_pixel_red[7 to 0] ref_pixel_green[7 to 0] ref_pixel_blue[7 to 0] black_lines[7 to 0] black_pixels[7 to 0] ref_pixel[7 to 0] ref_pixel[11 to 8] ref_line[7 to 0] ref_line[10 to 8]
1999 May 11
21
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
ADDRESS R/W 19 20 21 22 23 R R R R R
D7
D6
D5
D4
D3
D2
D1
D0 black_ pixels[8]
non_black_lines[7 to 0] non_black_lines[10 to 8] non_black_pixels[7 to 0] non_black_pixels[11 to 8]
General configuration 24 W intr_clear single_ no_ adc_mode memory_ mode yuv_clk_ mux memory_ init csm_ bypass reset_ reset_ input_path memory_ path frc_on blank_ screen reset_ proc_path power_ down
25
W
Clock distribution 26 27 28 29 30 31 32 W W W W W W W post_div_clock_p_high[3 to 0] post_div_clock_n_high[3 to 0] por_mclk pre_div_ enable post_div_ enable pre_div_ half_clock post_div_ half_clock pll_enable pll_pclk pll_mclk
pre_div_clock_p_high[3 to 0] pre_div_clock_n_high[3 to 0]
pre_div_clock_p_low[3 to 0] pre_div_clock_n_low[3 to 0] pre_div_clock_n_offs[3 to 0] post_div_clock_p_low[3 to 0] post_div_clock_n_low[3 to 0] post_div_clock_n_offs[3 to 0]
Input interface 33 W rgb_interl_ in_form_ on on field_ reverse v_offset[7 to 0] v_offset[10 to 8] h_offset[7 to 0] h_offset[11 to 8] v_length[7 to 0] v_length[10 to 8] h_length[7 to 0] h_length[11 to 8] clamp_on[7 to 0] clamp_off[7 to 0] gainc_on_delay[7 to 0] gainc_off_delay[7 to 0] rgb_proc_ adc_ on sample_ seq yuv_field_mode [1 and 0] gainc_pol clamp_pol vs_pol hs_pol
34 35 36 37 38 39 40 41 42 43 44 45 46
W W W W W W W W W W W W W
yuv_input_mode [1 and 0]
yuv_href_ pol
yuv_cref_ pol
1999 May 11
22
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
ADDRESS R/W Colour correction 47 W
D7
D6
D5
D4
D3
D2
D1
D0
red_prog
green_ prog
blue_prog
colour_ correction _on
48 49
W W(1)
colour_index[7 to 0] colour_value[7 to 0]
Memory interface/de-interlacing unit 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Scaler 75 W down_v_ scaler_ mem up_v_incr[7 to 0] up_v_incr[11 to 8] up_v_corr[6 to 0] up_h_incr[7 to 0] 23 up_v_ up_h_ up_v_ coeff_prog coeff_prog scaler_on up_h_ scaler_on down_v_ scaler_on down_h_ scaler_on W W W W W W W W W W W W W W W W W W W W W W W W W blank_colour_red[7 to 0] blank_colour_green[7 to 0] blank_colour_blue[7 to 0] line_length[7 to 0] line_length[11 to 8] field4_column[7 to 0] frame_length[7 to 0] frame_length[10 to 8] field3_column[7 to 0] field4_row[7 to 0] field4_row[10 to 8] field2_column[7 to 0] field3_row[7 to 0] field3_row[10 to 8] field1_column[7 to 0] field2_row[7 to 0] field2_row[10 to 8] SDRAM_burst_length_code[2 to 0] CAS_latency[2 to 0] t_RRD[3 to 0] t_WR[3 to 0] field1_row[7 to 0] field1_row[10 to 8] yuv422_ mode data_width[1 and 0] burst_seq_length[3 to 0] SDRAM_burst_length[3 to 0] t_RCD[3 to 0] t_RP[3 to 0] t_RC[3 to 0] deint_mode[1 and 0]
76 77 78 79 1999 May 11
W W W W
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
ADDRESS R/W 80 81 82 83 84 85 86 87 Panning unit 88 89 90 91 92 93 94 95 96 97 98 W W W W W W W W W W W W W W W W W W W(1)
D7
D6
D5
D4
D3
D2
D1
D0
up_h_incr[11 to 8] up_h_corr[6 to 0] down_v_incr[5 to 0] down_v_corr[6 to 0] down_h_incr[5 to 0] down_h_corr[6 to 0] coeff_index[5 to 0] coeff_value[6 to 0]
pic_v_offset[7 to 0] pic_v_offset[10 to 8] pic_h_offset[7 to 0] pic_h_offset[11 to 8] out_v_size[7 to 0] out_v_size[10 to 8] out_h_size[7 to 1] out_h_size[11 to 8] border_colour_red[7 to 0] border_colour_green[7 to 0] border_colour_blue[7 to 0] 0
OSD overlay port 99 W ovl_clk_ pol ovl_act_ pol ovl_vs_ pol ovl_hs_ pol clk_ gating_on sample_ edge ovl_ syncs_ active ovl_ insert_ active
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115
W W W W W W W W W W W W W W W W
ovl_hs_start[7 to 0] ovl_hs_start[10 to 8] ovl_hs_length[7 to 0] ovl_hs_length[10 to 8] ovl_hs_latency[7 to 0] ovl_h_length[7 to 0] ovl_h_length[10 to 8] ovl_v_offset[7 to 0] ovl_v_offset[10 to 8] ovl_v_length[7 to 0] ovl_v_length[10 to 8] ovl_vs_start[7 to 0] ovl_vs_start[10 to 8] ovl_colour0_red[7 to 0] ovl_colour0_green[7 to 0] ovl_colour0_blue[7 to 0]
1999 May 11
24
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
ADDRESS R/W 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 W W W W W W W W W W W W W W W W W W W W W
D7
D6
D5
D4
D3
D2
D1
D0
ovl_colour1_red[7 to 0] ovl_colour1_green[7 to 0] ovl_colour1_blue[7 to 0] ovl_colour2_red[7 to 0] ovl_colour2_green[7 to 0] ovl_colour2_blue[7 to 0] ovl_colour3_red[7 to 0] ovl_colour3_green[7 to 0] ovl_colour3_blue[7 to 0] ovl_colour4_red[7 to 0] ovl_colour4_green[7 to 0] ovl_colour4_blue[7 to 0] ovl_colour5_red[7 to 0] ovl_colour5_green[7 to 0] ovl_colour5_blue[7 to 0] ovl_colour6_red[7 to 0] ovl_colour6_green[7 to 0] ovl_colour6_blue[7 to 0] ovl_colour7_red[7 to 0] ovl_colour7_green[7 to 0] ovl_colour7_blue[7 to 0]
On screen display 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 W W W W W W W W W W W W W W W W W osd_v_size[5 to 0] osd_h_size[5 to 0] osd_fg_colour0_red[7 to 0] osd_fg_colour0_green[7 to 0] osd_fg_colour0_blue[7 to 0] osd_fg_colour1_red[7 to 0] osd_fg_colour1_green[7 to 0] osd_fg_colour1_blue[7 to 0] osd_fg_colour2_red[7 to 0] osd_fg_colour2_green[7 to 0] osd_fg_colour2_blue[7 to 0] osd_fg_colour3_red[7 to 0] osd_h_offset[7 to 0] osd_h_offset[11 to 8] osd_v_offset[7 to 0] osd_v_offset[10 to 8] zoom2 char_size osd_ active
1999 May 11
25
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
ADDRESS R/W 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W
D7
D6
D5
D4
D3
D2
D1
D0
osd_fg_colour3_green[7 to 0] osd_fg_colour3_blue[7 to 0] osd_fg_colour4_red[7 to 0] osd_fg_colour4_green[7 to 0] osd_fg_colour4_blue[7 to 0] osd_fg_colour5_red[7 to 0] osd_fg_colour5_green[7 to 0] osd_fg_colour5_blue[7 to 0] osd_fg_colour6_red[7 to 0] osd_fg_colour6_green[7 to 0] osd_fg_colour6_blue[7 to 0] osd_fg_colour7_red[7 to 0] osd_fg_colour7_green[7 to 0] osd_fg_colour7_blue[7 to 0] osd_bg_colour0_red[7 to 0] osd_bg_colour0_green[7 to 0] osd_bg_colour0_blue[7 to 0] osd_bg_colour1_red[7 to 0] osd_bg_colour1_green[7 to 0] osd_bg_colour1_blue[7 to 0] osd_bg_colour2_red[7 to 0] osd_bg_colour2_green[7 to 0] osd_bg_colour2_blue[7 to 0] osd_bg_colour3_red[7 to 0] osd_bg_colour3_green[7 to 0] osd_bg_colour3_blue[7 to 0] osd_bg_colour4_red[7 to 0] osd_bg_colour4_green[7 to 0] osd_bg_colour4_blue[7 to 0] osd_bg_colour5_red[7 to 0] osd_bg_colour5_green[7 to 0] osd_bg_colour5_blue[7 to 0] osd_bg_colour6_red[7 to 0] osd_bg_colour6_green[7 to 0] osd_bg_colour6_blue[7 to 0] osd_bg_colour7_red[7 to 0] osd_bg_colour7_green[7 to 0] osd_bg_colour7_blue[7 to 0] osd_fg_ colour7_ transp osd_fg_ colour6_ transp osd_fg_ colour5_ transp osd_fg_ colour4_ transp 26 osd_fg_ colour3_ transp osd_fg_ colour2_ transp osd_fg_ colour1_ transp osd_fg_ colour0_ transp
1999 May 11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
ADDRESS R/W 193 W
D7 osd_fg_ colour7_ alpha osd_bg_ colour7_ transp osd_bg_ colour7_ alpha
D6 osd_fg_ colour6_ alpha osd_bg_ colour6_ transp osd_bg_ colour6_ alpha
D5 osd_fg_ colour5_ alpha osd_bg_ colour5_ transp osd_bg_ colour5_ alpha
D4 osd_fg_ colour4_ alpha osd_bg_ colour4_ transp osd_bg_ colour4_ alpha
D3 osd_fg_ colour3_ alpha osd_bg_ colour3_ transp osd_bg_ colour3_ alpha
D2 osd_fg_ colour2_ alpha osd_bg_ colour2_ transp osd_bg_ colour2_ alpha
D1 osd_fg_ colour1_ alpha osd_bg_ colour1_ transp osd_bg_ colour1_ alpha
D0 osd_fg_ colour0_ alpha osd_bg_ colour0_ transp osd_bg_ colour0_ alpha
194
W
195
W
On screen display window 196 197 198 199 W W W W(1) char_appearance [1 and 0] cursor_row[5 to 0] cursor_column[5 to 0] char_bg_colour[2 to 0] char_fg_colour[2 to 0]
char_code[6 to 0]
On screen display character matrix 200 201 W char_code[6 to 0] W(1) char_def[7 to 0]
TFT display interface 202 W vsync_pol hsync_pol de_pol clk_pol single_ pixel_ output active_ctrl
203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 1999 May 11
W W W W W W W W W W W W W W W W W W W
line_sync
sync_de_ act
out_if_ enable
blank_tft
sync_ mode
blank_ctrl
border_ ctrl
h_len_blank[7 to 0] h_len_blank[10 to 8] h_len_border[7 to 0] h_len_border[10 to 8] h_len_active[7 to 0] h_len_active[10 to 8] v_end[7 to 0] v_end[10 to 8] v_start[7 to 0] v_start[10 to 8] v_active[7 to 0] v_active[10 to 8] h_vs_start[7 to 0] h_vs_start[10 to 8] h_vs_end[7 to 0] h_vs_end[10 to 8] h_hs_start[7 to 0] h_hs_start[10 to 8] 27
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
ADDRESS R/W 222 223 224 225 226 227 228 229 230 231 232 233 Note W W W W W W W W W W W W
D7
D6
D5
D4
D3
D2
D1
D0
h_hs_end[7 to 0] h_hs_end[10 to 8] h_de_start[7 to 0] h_de_start[10 to 8] h_de_end[7 to 0] h_de_end[10 to 8] h_active_start[7 to 0] h_active_start[10 to 8] v_vs_end[7 to 0] v_vs_end[10 to 8] h_max_len[7 to 0] h_max_len[10 to 8]
1. Register does not work with register address auto-increment, but with incrementing the address on which the operation is performed. Table 8 Detailed description of programming registers NAME State IIC TEST REGISTER IIC test register STATE REGISTER Interrupt state Interrupt active Interrupt not active RGB mode detection SYNC DETECT REGISTER Hsync presence Hsync present Hsync not present Vsync presence Vsync present Vsync not present Hsync polarity Negative Hsync Positive Hsync Vsync polarity Negative Vsync Positive Vsync 4 R D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 3 R D0 logic 0 logic 1 2 R/W D7 to D0 SUBADDRESS R/W DATA
1999 May 11
28
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME VERTICAL FRAME RESOLUTION Number of lines between two Vsyncs HORIZONTAL FRAME RESOLUTION Number of clocks between two Hsyncs RGB auto adjustment REFERENCE LINE POSITION Reference line for auto adjustment measurements REFERENCE PIXEL POSITION Reference pixel for auto adjustment measurements REFERENCE COLOUR Colour for selecting black or non-black pixels REFERENCE PIXEL COLOUR RED COMPONENT Red colour component of reference pixel REFERENCE PIXEL COLOUR GREEN COMPONENT Green colour component of reference pixel REFERENCE PIXEL COLOUR BLUE COMPONENT Blue colour component of reference pixel BLACK LINES COUNTER Number of black lines after Vsync BLACK PIXELS COUNTER Number of black pixels after Hsync NON-BLACK LINES COUNTER Number of non-black lines after Vsync NON-BLACK PIXELS COUNTER Number of non-black pixels after Hsync
SUBADDRESS
R/W
DATA
5 and 6
R
D10 to D0
7 and 8
R
D11 to D0
9 and 10
W
D10 to D0
11 and 12
W
D11 to D0
13
W
D7 to D0
14
R
D7 to D0
15
R
D7 to D0
16
R
D7 to D0
17
R
D7 to D0
18 and 19
R
D8 to D0
20 and 21
R
D10 to D0
22 and 23
R
D11 to D0
1999 May 11
29
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME General configuration CONFIGURATION REGISTER 1 Processing reset state Processing path not in reset state Processing path in reset state Memory reset state Memory path not in reset state Memory path in reset state Input reset state Input path not in reset state Input path in reset state External memory initialization No external memory initialization Start external memory initialization External memory configuration External memory present No external memory present External ADC configuration 2 ADCs connected 1 ADC connected Interrupt acknowledge No acknowledge Reset interrupt output to logic 1 CONFIGURATION REGISTER 2 Output interface Power-down mode Normal processing All outputs of output interface at LOW level Blank screen Normal data processing Blank screen generation after memory interface Output temporal dithering No temporal dithering of output data stream Temporal dithering of output data Colour space conversion matrix Conversion YUV to RGB enabled Straight RGB processing enabled YUV processing clock multiplexer Clock will be applied at pin VCLK Clock will be applied at pin MCLKI
SUBADDRESS
R/W
DATA
24
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 logic 1 D6 logic 0 logic 1
25
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1
1999 May 11
30
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME Clock distribution CLOCK MULTIPLEXING Memory clock generation Memory clock is taken from pin MCLKI Memory clock is
1 2
SUBADDRESS
R/W
DATA
26
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 logic 1 D6 logic 0 logic 1 D7 logic 0 logic 1
PLL clock
Panel clock generation Panel clock is equal system clock Panel clock is generated by PLL clock and post-divider PLL activation PLL disabled PLL enabled PLL post-divider precision
1 1 1 1 2 2
clock precision disabled clock precision enabled clock precision disabled clock precision enabled
PLL pre-divider precision
2 2
PLL post-divider activation PLL post-divider disabled PLL post-divider enabled PLL pre-divider activation PLL pre-divider disabled PLL pre-divider enabled External memory clock multiplexer Enable memory clock Use system clock as external memory clock PRE-DIVIDER P-COUNTER Pre-divider p-counter programming PRE-DIVIDER N-COUNTER Pre-divider n-counter programming PRE-DIVIDER N-OFFSET Pre-divider n-counter offset programming POST-DIVIDER P-COUNTER Post-divider p-counter programming POST-DIVIDER N-COUNTER Post-divider n-counter programming POST-DIVIDER N-OFFSET Post-divider n-counter offset programming 32 W 31 W 30 W 29 W 28 W 27 W
D7 to D0
D7 to D0
D3 to D0
D7 to D0
D7 to D0
D3 to D0
1999 May 11
31
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME Input interface GENERAL PROGRAMMING Hsync polarity Hsync is active LOW, line starts at rising edge of pin VHS Hsync is active HIGH, line starts at falling edge of pin VHS Vsync polarity Vsync is active LOW, line starts at rising edge of pin VVS Vsync is active HIGH, line starts at falling edge of pin VVS Clamp pulse polarity Pulse is active LOW Pulse is active HIGH Gain correction pulse polarity Pulse is active LOW Pulse is active HIGH ADC sample sequence ADC 0 is sampled first after Hsync (video input port A, B, C) ADC 1 is sampled first after Hsync (video input port D, E, F) RGB/YUV processing mode YUV processing enabled RGB processing enabled Input interface activation No data sampling Data sampling enabled Interlaced RGB mode Non-interlaced RGB processing Interlaced RGB processing
SUBADDRESS
R/W
DATA
33
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 logic 1 D6 logic 0 logic 1 D7 logic 0 logic 1
1999 May 11
32
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME INTERLACED MODE PROGRAMMING YUV CREF polarity YUV clock qualifier is active LOW YUV clock qualifier is active HIGH YUV HREF polarity Active data qualifier is active LOW Active data qualifier is active HIGH YUV format CCIR 656 4 : 1 : 1 format 4 : 2 : 2 format 4 : 4 : 4 format YUV field sampling mode All incoming frames are captured Capture alternating fields only Capture odd fields only Capture even fields only Field reverse flag Keep original odd field identification Change field identification VERTICAL SAMPLE OFFSET Vertical sample offset from Vsync HORIZONTAL SAMPLE OFFSET Horizontal sample offset from Hsync VERTICAL SAMPLE LENGTH Vertical sample window length HORIZONTAL SAMPLE LENGTH Horizontal sample window length CLAMP PULSE START Start of clamp pulse after active edge of Hsync CLAMP PULSE END End of clamp pulse after active edge of Hsync GAIN CORRECTION PULSE START DELAY Delay of start of GAINC pulse from first edge of Hsync GAIN CORRECTION PULSE END DELAY Delay of end of pulse GAINC from second edge of Hsync
SUBADDRESS
R/W
DATA
34
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D3 and D2 D3 = 0 and D2 = 0 D3 = 0 and D2 = 1 D3 = 1 and D2 = 0 D3 = 1 and D2 = 1 D5 and D4 D5 = 0 and D4 = 0 D5 = 0 and D4 = 1 D5 = 1 and D4 = 0 D5 = 1 and D4 = 1 D6 logic 0 logic 1
35 and 36
W
D10 to D0
37 and 38
W
D11 to D0
39 and 40
W
D10 to D0
41 and 42
W
D11 to D0
43
W
D7 to D0
44
W
D7 to D0
45
W
D7 to D0
46
W
D7 to D0
1999 May 11
33
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME Colour correction PROGRAMMING SELECTOR, ACTIVATION Colour correction activation Straight colour processing Colour substitution enabled Blue component programming Red component correction colour writing disabled Red component correction colour writing enabled Green component programming Red component correction colour writing disabled Red component correction colour writing enabled Red component programming Red component correction colour writing disabled Red component correction colour writing enabled COLOUR INDEX FOR LOOK-UP TABLE WRITING Colour component look-up table index COLOUR VALUE FOR LOOK-UP TABLE WRITING Colour component substitution value Memory interface/de-interlacing unit GENERAL CONFIGURATION De-interlacing mode No de-interlacing De-interlacing without filtering De-interlacing with spatial filtering De-interlacing with temporal filtering External memory data bus width 32 bits (two 16-bit channels) 48 bits (three 16-bit channels) 64 bits (four 16-bit channels) do not use Internal data path width RGB and YUV 4 : 4 : 4 processing YUV 4 : 2 : 2, YUV 4 : 1 : 1 and CCIR 656 processing ACCESS BURST LENGTH Number of bursts per read/write access to SDRAM SDRAM BURST LENGTH SDRAM burst length SDRAM initialization code for burst length
SUBADDRESS
R/W
DATA
47
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1
48
W
D7 to D0
49
W
D7 to D0
50
W
D1 and D0 D1 = 0 and D0 = 0 D1 = 0 and D0 = 1 D1 = 1 and D0 = 0 D1 = 1 and D0 = 1 D3 and D2 D3 = 0 and D2 = 0 D3 = 0 and D2 = 1 D3 = 1 and D2 = 0 D3 = 1 and D2 = 1 D4 logic 0 logic 1
51
W
D3 to D0
52
W
D3 to D0 D6 to D4
1999 May 11
34
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME SDRAM TIMING PARAMETER 1; SEE TABLE 14 Active to read or write delay (tRCD) in clocks CAS latency (CL) in clocks SDRAM TIMING PARAMETER 2; SEE TABLE 14 Precharge command period (tRP) in clocks Active bank A to active band B command (tRRD) in clocks SDRAM TIMING PARAMETER 3; SEE TABLE 14 Auto refresh, active command period (tRC) in clocks Write recovery time (tWR) in clocks FIELD 1 START ADDRESS (ROW) Start address of field 1 in external SDRAM memory (row) FIELD 1 START ADDRESS (COLUMN) Start address of field 1 in external SDRAM memory (column) FIELD 2 START ADDRESS (ROW) Start address of field 2 in external SDRAM memory (row) FIELD 2 START ADDRESS (COLUMN) Start address of field 2 in external SDRAM memory (column) FIELD 3 START ADDRESS (ROW) Start address of field 3 in external SDRAM memory (row) FIELD 3 START ADDRESS (COLUMN) Start address of field 3 in external SDRAM memory (column) FIELD 4 START ADDRESS (ROW) Start address of field 4 in external SDRAM memory (row) FIELD 4 START ADDRESS (COLUMN) Start address of field 4 in external SDRAM memory (column) OUTPUT FRAME LENGTH Vertical length of output frame after de-interlacing unit OUTPUT LINE LENGTH Horizontal length of output frame after de-interlacing unit BLANK COLOUR RED COMPONENT DEFINITION Red colour component for blank screen generation BLANK COLOUR GREEN COMPONENT DEFINITION Green colour component for blank screen generation BLANK COLOUR BLUE COMPONENT DEFINITION Blue colour component for blank screen generation
SUBADDRESS
R/W
DATA
53
W
D3 to D0 D6 to D4
54
W
D3 to D0 D7 to D4
55
W
D3 to D0 D7 to D4
56 and 57
W
D10 to D0
58
W
D7 to D0
59 and 60
W
D10 to D0
61
W
D7 to D0
62 and 63
W
D10 to D0
64
W
D7 to D0
65 and 66
W
D10 to D0
67
W
D7 to D0
68 and 69
W
D10 to D0
70 and 71
W
D11 to D0
72
W
D7 to D0
73
W
D7 to D0
74
W
D7 to D0
1999 May 11
35
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME Scaler SCALER CONFIGURATION Horizontal downscaler activation Horizontal downscaler disabled Horizontal downscaler enabled Vertical downscaler activation Vertical downscaler disabled Vertical downscaler enabled Horizontal upscaler activation Horizontal upscaler disabled Horizontal upscaler enabled Vertical upscaler activation Vertical upscaler disabled Vertical upscaler enabled Horizontal upscaling transition function programming Horizontal upscaling transition function writing disabled Horizontal upscaling transition function writing enabled Vertical upscaling transition function programming Vertical upscaling transition function writing disabled Vertical upscaling transition function writing enabled Line memory usage Line memory used by upscaling unit Line memory used by downscaling unit VERTICAL UPSCALE INCREMENT Increment for vertical upscaling VERTICAL UPSCALE CORRECTION Fraction of vertical upscaling increment (1100) HORIZONTAL UPSCALE INCREMENT Increment for horizontal upscaling HORIZONTAL UPSCALE CORRECTION Fraction of horizontal upscaling increment (1100) VERTICAL DOWNSCALE INCREMENT Increment for vertical downscaling VERTICAL DOWNSCALE CORRECTION Fraction of vertical downscaling increment (1100) HORIZONTAL DOWNSCALE INCREMENT Increment for horizontal downscaling
SUBADDRESS
R/W
DATA
75
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 logic 1 D6 logic 0 logic 1
76 and 77
W
D11 to D0
78
W
D6 to D0
79 and 80
W
D11 to D0
81
W
D6 to D0
82
W
D5 to D0
83
W
D6 to D0
84
W
D5 to D0
1999 May 11
36
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME HORIZONTAL DOWNSCALE CORRECTION Fraction of horizontal downscaling increment (1100) INDEX FOR COEFFICIENT TABLE WRITING Transition function look-up table index COEFFICIENT VALUE FOR LOOK-UP TABLE WRITING Values of transition function Panning unit VERTICAL PICTURE OFFSET Vertical input picture offset inside the output frame HORIZONTAL PICTURE OFFSET Horizontal input picture offset inside the output frame VERTICAL OUTPUT FRAME LENGTH Vertical output frame length HORIZONTAL OUTPUT FRAME LENGTH Horizontal output frame length BORDER COLOUR RED COMPONENT DEFINITION Red colour component for border generation BORDER COLOUR GREEN COMPONENT DEFINITION Green colour component for border generation BORDER COLOUR BLUE COMPONENT DEFINITION Blue colour component for border generation
SUBADDRESS
R/W
DATA
85
W
D6 to D0
86
W
D5 to D0
87
W
D6 to D0
88 and 89
W
D10 to D0
90 and 91
W
D11 to D0
92 and 93
W
D10 to D0
94 and 95
W
D11 to D0
96
W
D7 to D0
97
W
D7 to D0
98
W
D7 to D0
1999 May 11
37
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME OSD overlay port GENERAL CONFIGURATION OSD overlay port activation Overlay information will not be inserted into data stream Overlay information will be inserted into data stream Sync pulse generation No sync pulses will be generated Sync pulses will be generated Clock edge for sampling Data sampling at falling edge of clock at pin OVCLK Data sampling at rising edge of clock at pin OVCLK Clock gating OVCLK always enabled OVCLK enabled only during internal active video processing Horizontal sync polarity Active LOW horizontal sync pulse at pin OVHS Active HIGH horizontal sync pulse at pin OVHS Vertical sync polarity Active LOW vertical sync pulse at pin OVVS Active HIGH vertical sync pulse at pin OVVS Overlay port active pixel qualifier polarity Active LOW qualifier signal at pin OVACT Active HIGH qualifier signal at pin OVACT Overlay port clock polarity Sync pulse change with respect to falling edge at pin OVCLK Sync pulse change with respect to rising edge at pin OVCLK OVERLAY HORIZONTAL SYNC START Start of horizontal sync pulse with respect to left frame border OVERLAY HORIZONTAL SYNC LENGTH Length of horizontal sync pulse OVERLAY HORIZONTAL SYNC LATENCY Delay between start of horizontal sync and valid overlay data OVERLAY WINDOW HORIZONTAL LENGTH Horizontal length of overlay region OVERLAY WINDOW VERTICAL OFFSET Vertical offset of overlay region OVERLAY WINDOW VERTICAL LENGTH Vertical length of overlay region
SUBADDRESS
R/W
DATA
99
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 logic 1 D6 logic 0 logic 1 D7 logic 0 logic 1
100 and 101
W
D10 to D0
102 and 103
W
D10 to D0
104
W
D7 to D0
105 and 106
W
D10 to D0
107 and 108
W
D10 to D0
109 and 110
W
D10 to D0
1999 May 11
38
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME OVERLAY VERTICAL SYNC START Start of vertical sync pulse with respect to top frame border COLOUR 0 TO 7 RED COMPONENT DEFINITION Red colour component for overlay colour 0 to 7
SUBADDRESS
R/W
DATA
111 and 112
W
D10 to D0
113, 116, 119, 122, 125, 128, 131 and 134
W
D7 to D0
COLOUR 0 TO 7 GREEN COMPONENT DEFINITION Green colour component for overlay colour 0 to 7 114, 117, 120, 123, 126, 129, 132 and 135 W D7 to D0
COLOUR 0 TO 7 BLUE COMPONENT DEFINITION Blue colour component for overlay colour 0 to 7 115, 118, 121, 124, 127, 130, 133 and 136 W D7 to D0
On screen display GENERAL CONFIGURATION OSD activation OSD is not visible OSD is visible OSD character size 12 x 16 character matrix 24 x 24 character matrix OSD zoom No zooming of OSD window Zoom by 2 of OSD window OSD WINDOW VERTICAL OFFSET Vertical offset of OSD window from left frame border in pixel OSD WINDOW HORIZONTAL OFFSET Horizontal offset of OSD window from top frame border in pixel OSD WINDOW VERTICAL SIZE Vertical size of OSD window in characters OSD WINDOW HORIZONTAL SIZE Horizontal size of OSD window in characters FOREGROUND COLOUR 0 TO 7 RED COMPONENT DEFINITION Red colour component for foreground colour 0 to 7 144, 147, 150, 153, 156, 159, 162 and 165 W D7 to D0 143 W D5 to D0 142 W D5 to D0 140 and 141 W D11 to D0 138 and 139 W D10 to D0 137 W D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1
1999 May 11
39
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME FOREGROUND COLOUR 0 TO 7 GREEN COMPONENT DEFINITION Green colour component for foreground colour 0 to 7
SUBADDRESS
R/W
DATA
145, 148, 151, 154, 157, 160, 163 and 166
W
D7 to D0
FOREGROUND COLOUR 0 TO 7 BLUE COMPONENT DEFINITION Blue colour component for foreground colour 0 to 7 146, 149, 152, 155, 158, 161, 164 and 167 W D7 to D0
BACKGROUND COLOUR 0 TO 7 RED COMPONENT DEFINITION Red colour component for background colour 0 to 7 168, 171, 174, 177, 180, 183, 186 and 189 W D7 to D0
BACKGROUND COLOUR 0 TO 7 GREEN COMPONENT DEFINITION Green colour component for background colour 0 to 7 169, 172, 175, 178, 181, 184, 187 and 190 W D7 to D0
BACKGROUND COLOUR 0 TO 7 BLUE COMPONENT DEFINITION Blue colour component for background colour 0 to 7 170, 173, 176, 179, 182, 185, 188 and 191 W D7 to D0
FOREGROUND TRANSPARENT COLOUR DEFINITION Foreground colour transparency Foreground colour is not transparent Foreground colour is transparent FOREGROUND ALPHA BLENDING COLOUR DEFINITION Foreground colour alpha blending Foreground colour is not alpha blendable Foreground colour is alpha blendable BACKGROUND TRANSPARENT COLOUR DEFINITION Background colour transparency Background colour is not transparent Background colour is transparent BACKGROUND ALPHA BLENDING COLOUR DEFINITION Background colour alpha blending Background colour is not alpha blendable Background colour is alpha blendable 195 W D7 to D0 logic 0 logic 1 194 W D7 to D0 logic 0 logic 1 193 W D7 to D0 logic 0 logic 1 192 W D7 to D0 logic 0 logic 1
1999 May 11
40
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME On screen display window CURSOR POSITION 1 Cursor row CURSOR POSITION 2 Cursor column CHARACTER APPEARANCE Foreground colour code Background colour code Character appearance Picture information will be overwritten by OSD data Transparency of OSD transparent colours 1 : 1 alpha blending of OSD alpha colours 1 : 2 alpha blending of OSD alpha colours CHARACTER CODE Code of character to be placed at cursor position On screen display character matrix CHARACTER CODE Code of character to be defined CHARACTER PATTERN Character definition pattern TFT display interface GENERAL CONFIGURATION 1 Output width Double pixel output (48 bits) Single pixel output (24 bits) Output clock polarity Data output with respect to falling edge of pin PCLK Data output with respect to rising edge of pin PCLK Data qualifier polarity Active LOW pin PDE Active HIGH pin PDE Horizontal sync polarity Active LOW horizontal sync at pin PHS Active HIGH horizontal sync at pin PHS Vertical sync polarity Active LOW vertical sync at pin PVS Active HIGH vertical sync at pin PVS
SUBADDRESS
R/W
DATA
196
W
D5 to D0
197
W
D5 to D0
198
W
D2 to D0 D5 to D3 D7 and D6 D7 = 0 and D6 = 0 D7 = 0 and D6 = 1 D7 = 1 and D6 = 0 D7 = 1 and D6 = 1
199
W
D6 to D0
200
W
D6 to D0
201
W
D7 to D0
202
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1
1999 May 11
41
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME GENERAL CONFIGURATION 2 Line length controlling in active video region Line length controlling disabled Line length controlling enabled Line length controlling in border region Line length controlling disabled Line length controlling enabled Line length controlling in top blanking region Line length controlling disabled Line length controlling enabled Output interface mode Free running output interface timing (external SDRAM required) Synchronous output interface timing (without external SDRAM) Blanking mode Normal operating mode All data outputs are at LOW level (black colour) Output interface enabling Output interface disabled, no data processing Output interface enabled, normal data processing Data qualifier generation mode Disable pulse generation at pin PDE during vertical syncs Enable pulse generation at pin PDE during vertical syncs Line synchronization Normal mode Do not use HORIZONTAL LINE LENGTH IN BLANKING REGION Horizontal line length in blanking region HORIZONTAL LINE LENGTH IN BORDER REGION Horizontal line length in border region HORIZONTAL LINE LENGTH IN ACTIVE VIDEO REGION Horizontal line length in active video region VERTICAL FRAME END Vertical frame length VERTICAL BORDER REGION START Vertical start of border region VERTICAL ACTIVE VIDEO REGION START Vertical start of active video region HORIZONTAL DELAY OF START OF VERTICAL SYNC Horizontal start delay of vertical sync pulse at pin PVS 1999 May 11 42
SUBADDRESS
R/W
DATA
203
W
D0 logic 0 logic 1 D1 logic 0 logic 1 D2 logic 0 logic 1 D3 logic 0 logic 1 D4 logic 0 logic 1 D5 logic 0 logic 1 D6 logic 0 logic 1 D7 logic 0 logic 1
204 and 205
W
D10 to D0
206 and 207
W
D10 to D0
208 and 209
W
D10 to D0
210 and 211
W
D10 to D0
212 and 213
W
D10 to D0
214 and 215
W
D10 to D0
216 and 217
W
D10 to D0
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
NAME HORIZONTAL DELAY OF END OF VERTICAL SYNC Horizontal end delay of vertical sync pulse at pin PVS HORIZONTAL SYNC PULSE START Start of horizontal sync pulse at pin PHS HORIZONTAL SYNC PULSE END End of horizontal sync pulse at pin PHS DATA QUALIFIER START Start of border region and horizontal data qualifier at pin PDE DATA QUALIFIER END End of border region and horizontal data qualifier at pin PDE HORIZONTAL ACTIVE REGION START Start of horizontal active video region VERTICAL SYNC PULSE END Vertical sync pulse end at pin PVS MAXIMUM HORIZONTAL LINE LENGTH Maximum reachable line length for length controlling 8.2 8.2.1 Clock management CLOCK GENERATION AND MULTIPLEXING
SUBADDRESS
R/W
DATA
218 and 219
W
D10 to D0
220 and 221
W
D10 to D0
222 and 223
W
D10 to D0
224 and 225
W
D10 to D0
226 and 227
W
D10 to D0
228 and 229
W
D10 to D0
230 and 231
W
D10 to D0
232 and 233
W
D10 to D0
For normal operation the SAA6721E uses two clock inputs; pin VCLK and pin CLK. VCLK is used as the sample clock provided by the external ADCs or decoder. The frequency and the sample edges of this clock depend on the number of ADCs connected, or on the video dot clock: * 1 ADC mode: maximum VCLK frequency is 150 MHz * 2 ADC mode: maximum VCLK frequency is 75 MHz. The clock from pin CLK is used as an internal reference, and it is the source clock for the internal PLL. The memory clock MCLKO and panel clock PCLK are derived from the PLL (see Fig.11): CLK MCLKO = ---------- x 16 N CLK 32 PCLK = ---------- x ----N M Where N = pre-divider ratio, M = post-divider ratio and CLK 5 MHz ---------- 8 MHz N
It is possible to drive the memory clock output directly without the internal PLL via pin MCLKI. To achieve this the programming flag pll_mclk must be set to logic 0. The same is possible for the panel output clock. Therefore the system clock CLK is used directly. The system clock is controlled by pll_pclk which must be set to logic 0.
1999 May 11
43
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
handbook, full pagewidth
MCLKI MCLKO CLK PRE-DIVIDER PLL x 32 POST-DIVIDER PCLK
/2
MHB251
Fig.11 Clock generator.
8.2.2
CLOCK DIVIDER
The pre- and post-dividers are implemented in such a way, that they support dividing ratios of 0.5 steps in an interval from 1.5 to 10.5. All further dividing ratios are in steps of 1.0; see Fig.12 and Table 9. Programming of the clock dividers must be done using the registers 26 to 32. It is necessary that the clock dividers must be disabled before programming and be enabled afterwards. This can be done with pre_div_enable and post_div_enable.
handbook, full CLK pagewidth
CLK/4
CLK/4.5
CLK/5
CLK/5.5
MHB252
Fig.12 Clock waveforms.
Table 9
Clock divider programming RATIO 1.5 2.0 2.5 3.0 3.5 P-COUNTER (HEX) 10 00 30 10 41 N-COUNTER (HEX) 10 00 30 10 41 44 N-OFFSET COUNTER (HEX) 1 0 2 0 3 HALF CLK 1 0 1 1 1
1999 May 11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
RATIO 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 31.0 32.0
P-COUNTER (HEX) 11 61 21 72 22 92 32 A3 33 C3 43 D4 44 F4 54 55 65 66 76 77 87 88 98 99 A9 AA BA BB CB CC DC DD ED EE FE FF
N-COUNTER (HEX) 00 61 21 72 00 92 32 A3 00 C3 43 D4 00 F4 54 00 65 00 76 00 87 00 98 00 A9 00 BA 00 CB 00 DC 00 ED 00 FE 00
N-OFFSET COUNTER (HEX) 0 4 0 5 0 6 0 7 0 8 0 9 0 A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HALF CLK 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1999 May 11
45
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.3 8.3.1 RGB/YUV input interface SAMPLING MODE Table 10 Clock relationships NUMBER OF ADCs 1 2
1
SAA6721E
VCLK dot clock
2
The input interface allows sampling of RGB or YUV data. Because of that two different modes must be supported: RGB data sampling and YUV data sampling. The flag rgb_proc_on selects RGB mode sampling if asserted. If the flag is not asserted YUV data is selected. Sampling of interlaced RGB data is enabled by rgb_interl_on. 8.3.2 RGB DATA SAMPLING
VCLK SAMPLE EDGE positive both
dot clock
Sampling is done on the rising edge or on both edges of VCLK depending on the number of ADCs. The sample window is defined by v_offset, h_offset, v_length, and h_length. The offset counters start counting from the second edge of their reference signals, i.e. VVS for vertical offset and VHS for horizontal offset. Figure 13 shows the horizontal offset. The polarities of the sync signals are given with vs_pol and hs_pol. The vertical sample offset is given in lines and the horizontal offset is measured in pixels. The width of the sample window is defined by the length counters. The vertical width is measured in lines and the horizontal width in pixels, but only even pixel numbers are allowed. The sample clock for the ADCs is always VCLK, but in dual ADC mode this clock is half the pixel clock. Because of that, in dual ADC mode, both clock edges are used to sample data by the ADCs.
In single ADC mode, with each VCLK clock, a pixel must be sampled from port A. In dual ADC mode, at each VCLK clock edge, a pixel must be sampled alternating from port A or B. The flag adc_sample_seq selects from which port data sampling starts after the active edge of the horizontal synchronization pulse. 8.3.3 CLAMP PULSE GENERATION
The clamp pulse is generated with respect to half the dot clock. The counters values responsible for switching the clamp pulse on or off are clamp_on and clamp_off. Both start counting from the second edge of VHS. The polarity of CLAMP is given with clamp_pol.
handbook, full pagewidth
VHS
h_offset n 0 1 23 4 5
h_length
RGB data
MHB253
Fig.13 RGB data sampling.
1999 May 11
46
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.3.4 GAIN CORRECTION PULSE GENERATION
SAA6721E
The GAINC signal is the delayed horizontal sync pulse (VHS). It is delayed with respect to half the dot clock. The first edge of VHS is delayed by gainc_on_delay and the second edge by gainc_off_delay (see Fig.14). The polarity is programmed by gainc_pol.
handbook, full pagewidth
VHS
clamp_off clamp_on RGB data
GAINC
gainc_on_delay gainc_off_delay CLAMP
MHB254
Fig.14 Gain adjustment and clamp pulse generation.
8.3.5
YUV DATA SAMPLING
Table 11 YUV input modes yuv_input_mode[1 and 0] 0 1 2 3 DESCRIPTION YUV 4 : 2 : 2 with CCIR 656 codes YUV 4 : 1 : 1 YUV 4 : 2 : 2 YUV 4 : 4 : 4
In YUV mode the input interface receives digital YUV encoded video data from an external video decoder. The video data can be in 4 : 4 : 4, 4 : 2 : 2, 4 : 1 : 1, or YUV 4 : 2 : 2 with CCIR 656 codes. For the 4 : 4 : 4, 4 : 2 : 2, and 4 : 1 : 1 formats the reference signals VVS and VHS must be considered to identify the frames. The polarity of these signals is programmable with vs_pol and hs_pol. The region of valid video data and the start point for the UV sequence is defined by HREF applied at pin VPD6. External reference signals are needed for sampling the YUV 4 : 4 : 4, 4 : 2 : 2 and 4 : 1 : 1 data. If CCIR 656 data is to be sampled, all external reference signals are ignored, because their information is coded into the data stream. All information about active video, blanking and field ID is taken from the CCIR 656 codes. The selection of the input format is done by yuv_input_mode as shown in Table 11.
Data sampling occurs in relation to horizontal and vertical offset counters, and horizontal and vertical length counters. They are the same as for programming the RGB input, v_offset, h_offset, v_length, and h_length. All offset and length values are relative to the whole frame, and not to odd or even fields (see Fig.15).
1999 May 11
47
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
handbook, full pagewidth
odd line even line
line number 1 314 2 315 3 316 4 317 5 318 6 319 7 320 8 321 9 322 10 323 11 324 12 325
MHB255
Vsync end
offset 0 1 2 3 4 5 6 7 8 9 10
Fig.15 Line sampling.
8.3.5.1
Field capturing
8.3.5.2
YUV clocking
Another problem that must be considered is frame dropping. It is possible that the connected video source only provides either odd or even frames, or that the video source drops frames. Therefore the input interface must process the incoming video stream in several ways, as shown in Table 12. Table 12 Field capture modes yuv_field_mode[1 and 0] 0 1 DESCRIPTION all incoming frames are captured after an odd frame the next even frame will be captured, and vice versa capture only odd frames capture only even frames
VCLK, or alternatively the clock from MCLKI, is used for clocking the input interface in YUV mode and the data path behind the external clock. This second port will be used if yuv_clk_mux is set to logic 1. The external clock is the line-locked video clock from the video decoder. This clock is gated by CREF and applied at pin VPD7. Data is only to be sampled if this signal is asserted. Alternatively the line-locked video clock divided by two can be used (if provided by the decoder). In this event CREF must be tied to logic 1 or logic 0 depending on its programmed polarity.
2 3
1999 May 11
48
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.4 Video mode and synchronization signal detection 8.5
SAA6721E
Memory interface and de-interlacer unit
The SAA6721E can be used to build up multi-sync systems using an external microcontroller. Therefore information about the input resolution and timing are provided (see Tables 7 and 8). The flags pos_vsync and pos_hsync show the polarity of the synchronization signals at VVS and VHS. If they are set to logic 1 they are active HIGH, and their active edge is the falling edge. If these flags are set to logic 0, they are active LOW. For detecting Video Electronic Standard Association (VESA) Power-down modes or a not connected input, the presence of the synchronization signals will be detected: it can be read via no_vsync, and no_hsync. These flags are active HIGH. The timing of the applied RGB video input can be taken from v_lines reporting the number of lines of a full frame. The horizontal timing can be calculated from h_clocks. This register shows the length of a line in numbers of reference clock periods. The reference clock is equal to the panel clock PCLK in double pixel output mode (48 bits in parallel), or it is half the panel clock PCLK in single pixel output mode (24 bits in parallel). If one of the above mentioned flags or counters changes its value, it can be assumed that a new graphics mode has been applied. In this case an interrupt at pin INT will be generated. This port is active LOW. The reset can be cleared by writing a logic 1 to intr_clear at address 24. For adjusting the RGB input interface to a new graphics mode, the registers of the section RGB auto adjustment are to be used. With this auto adjustment support it is possible to measure the number of blanking pixels and lines between the end of the synchronization pulses and the active video. The horizontal and vertical back porch blanking can be read out at black_pixels and black_lines. The number of active pixels or lines will be reported from non_black_pixels and non_black_lines. The first value should be used for tuning the sample clocks PLL so that this value corresponds to the number of pixels to be sampled horizontally in this specific graphics mode. To distinguish between blanking and active video ref_colour is used. If the sample values of all three colour components are below this value the pixel is treated as a blanking pixel, otherwise it is treated as active video. Additionally a reference pixel can be defined with ref_line and ref_pixel. The R, G, and B components of this pixel are sampled and available at ref_pixel_red, ref_pixel_green, and ref_pixel_blue. They can be used for fine tuning the external PLL in frequency and phase and for colour gain adjustment.
The SAA6721E features a 64 bits wide synchronous DRAM interface. Both SDRAM and SGRAM devices can be used. There is no difference in programming when using SDRAM or SGRAM devices. The only thing that must be considered is the amount of frame buffer memory, which must be enough for the specific application. Depending on the kind of input data stream the memory interface must be switched to YUV 4 : 2 : 2 or YUV 4 : 1 : 1 mode by setting yuv422_mode to logic 1 to enable 16 bits per pixel processing. If this flag is set to logic 0, 24 bits per pixel are used which is needed for RGB and YUV 4 : 4 : 4 processing. If not the whole bandwidth of the 64 bits wide data bus is needed, the data bus can be downsized to 48 or 32 bits. This is done with the parameter data_width, see Table 13. Table 13 Data bus width data_width[1 and 0] 0 1 2 PROGRAMMED BUS WIDTH (BITS) 32 48 64
Since the different timing parameters of various RAM device types are different, all important timing values are programmable and must be set-up according to the used RAM types. To reach a high effective bandwidth all access to the external memory is organized in bursts. The larger the number of subsequent read or write accesses the higher the effective bandwidth. An effective bandwidth of 91% can be reached by doing 64 words burst accesses. The RAM devices support a maximum internal burst length of 8 words only, so 8 of these bursts must be run subsequently. This can be programmed by setting up the RAM with SDRAM_burst_length_code taken from the specification data of the SDRAM or SGRAM. The memory interface must be programmed to 64 words bursts by programming the RAM burst length SDRAM_burst_length to 8, and the number of these bursts in burst_seq_length to 8. The internal structure of the SAA6721E is optimized for 64 words bursts.
1999 May 11
49
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.5.1 MEMORY INTERFACE LIMITATIONS
SAA6721E
The timing parameters of the memory access can be programmed to fulfil the timing restrictions of several SDRAM or SGRAM devices. But there are some limitations, as shown in Table 14. Table 14 Memory interface limitations TIMING SYMBOL CAS latency tRCD tRRD tRP tWR tRC SDRAM_burst_length burst_seq_length tRSC PARAMETER Column Address Strobe (CAS) latency activate to command delay; Row Address Strobe (RAS) to CAS delay RAS to RAS bank activity delay RAS precharge time write recovery time RAS cycle time must be supported by SDRAM must be an even number Register Set Cycle (RSC) mode time internally defined; cannot be changed INITIALIZATION OF EXTERNAL MEMORY tRRD tRCD; proposal is tRRD = tRCD + 1 CONDITIONS MINIMUM VALUE (CLOCK PERIODS) 2 2 3 3 1 3 2 2 =8
8.5.2
All SGRAM and SDRAM devices must be powered-up and initialized correctly. The SAA6721E memory interface is implemented to fulfil the INTEL PC100 SDRAM specification. Table 15 shows the required programming steps to initialize the memory correctly. Table 15 Memory initialization programming STEP 1 2 3 4 5 8.5.3 SAA6721E Power-on reset set-up timing parameters start memory initialization with setting memory_init set-up all other parameters release internal memory reset together with other internal resets ACTION REGISTERS - 51 to 55 24 50 to 74 24
FRAME AND FIELD MEMORY
The memory interface acts as a decoupling unit to adapt the different frame rates at the video input to the panel output. The external memory is also used for the de-interlacing unit which reconstructs the frames from odd and even fields in interlaced mode. The algorithm of de-interlacing can be selected by deint_mode (see Table 16).
1999 May 11
50
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
Table 16 De-interlacing modes deint_mode[1 and 0] 0 1 2 3 ALGORITHM no de-interlacing and no filtering de-interlacing without filtering de-interlacing with spatial filtering de-interlacing with temporal filtering
SAA6721E
MEMORY NEEDS 1 frame buffer 2 field buffers 2 field buffers 4 field buffers
De-interlacing mode 0 must be selected for non-interlaced input of RGB or YUV. Only one memory area is needed, whose start address must be programmed into field1_row and field1_column. Normally this should be logic 0 for both values. All other modes need more than one memory area. So the other field start addresses must be programmed (see Fig.16).
handbook, full pagewidth
field1_row/column
field1_row/column ODD FIELD
field1_row/column ODD FIELD field2_row/column
field2_row/column EVEN FIELD field3_row/column
EVEN FIELD
ODD FIELD deint_mode 0 field4_row/column EVEN FIELD
deint_mode 1/2
MHB256
deint_mode 3
Fig.16 Memory usage for de-interlacing.
The memory interface addresses alternately the two banks of the SDRAM or SGRAM devices. So the memory needs for the field stores must be calculated from the following formula: bytes_per_pixel field_memory_size[18 to 0] = number_of_pixels x ---------------------------------------------------------------------- , where 2 x data_bus_width (bytes) * number_of_pixels depends on the input resolution and whether it is an odd or even field * bytes_per_pixel is 2 for YUV 4 : 2 : 2 and YUV 4 : 1 : 1; 3 for YUV 4 : 4 : 4 and RGB. All memory addresses must be transformed into row and column addresses used by DRAMs. The column address is formed by the 8 LSBs (field_memory_size[7 to 0]), and the row address by all the other address bits (field_memory_size[18 to 8]). The column address must be aligned to the number of internal DRAM bursts, normally in steps of 8 (0, 8, 16, etc.).
1999 May 11
51
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
The values given in Table 17 can be used for frame resolutions up to 720 x 576 pixels which complies to the 625 line/50 Hz mode. Table 17 Field start address values FIELD Field1 row/column Field2 row/column Field3 row/column Field4 row/column 8.5.4 FRAME RECOVERY VALUE (HEX) 000/0 08D/0 100/0 180/0
SAA6721E
Setting up the desired downscaling ratios is achieved by programming the scaling increments down_v_incr, down_v_corr, and down_h_incr, down_h_corr. This must be done for both vertical and horizontal scaling. number_of_output_pixels incr = ------------------------------------------------------------------ x 64 = xx.yy number_of_input_pixels Where xx is equivalent to down_v_incr or down_h_incr and yy is the fraction of the result in 1100. This is the value for programming the increment correction values down_v_corr and down_h_corr. Example: SXGA XGA 1024 Horizontal: ------------ x 64 = 51.20 1280 This means down_h_incr = 51 and down_h_corr = 20. 768 Vertical: ------------ x 64 = 48.00 1024 This means down_v_incr = 48 and down_v_corr = 0. 8.6.2 UPSCALING
During de-interlacing and also in mode 0, output frames with the right vertical and horizontal dimensions must be generated. Since size information is not stored in the external memory, the output frame resolution must be programmed into the registers frame_length and line_length. The first value gives the vertical resolution, and the second the horizontal resolution in pixels. If no downscaler is used, these values can be taken directly from the input interface. If downscaling is activated, the size of the de-interlacer output frame must be calculated from the RGB input frame size divided by the downscaling factors. If no valid data stream is applied at the RGB/YUV input interface, the de-interlacer is able to generate a picture by itself. This will be enabled with blank_screen at address 25. The colour of this frame is defined by blank_colour_red, blank_colour_green, and blank_colour_blue. 8.6 Scaling
The upscaler must be activated by up_v_scaler_on and up_h_scaler_on. To use the line memory for upscaling, down_v_scaler_mem must be set to logic 0. To set-up the zoom factor, the scaling increments up_v_incr, up_v_corr, up_h_incr, and up_h_corr must be programmed. number_of_output_pixels incr = ------------------------------------------------------------------ x 64 = xx.yy number_of_input_pixels Where xx is equivalent to up_v_incr or up_h_incr and yy is the fraction of the result in 1100. This is the value for programming the increment correction values up_v_corr and up_h_corr. Example: XGA SXGA 1280 Horizontal: ------------ x 64 = 80.00 1024 This means up_h_incr = 80 and up_h_corr = 0. 1024 Vertical: ------------ x 64 = 85.33 768 This means up_v_incr = 85 and up_v_corr = 33.
Two different scaling units are implemented to perform both up and downscaling. The downscaling engine, which is located before the memory interface, and the upscaling engine after the memory interface. 8.6.1 DOWNSCALING
If the downscaler is to be used, it must be enabled by setting flags down_v_scaler_on and down_h_scaler_on. For vertical scaling a line memory buffer is needed. This memory must be switched to downscaling mode by setting down_v_scaler_mem to logic 1 because only one is available.
1999 May 11
52
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.6.3 UPSCALER TRANSITION FUNCTION 8.7 Panning unit
SAA6721E
A special feature of the zooming algorithm is a free programmable transition function which allows smoothing or sharpening of the transition between pixels that have been calculated. This function will be stored in a look-up table, containing 64 words of 7 bits; thus a function of 64 points with a resolution from 0 to 64 can be programmed. Programming is performed using the registers coeff_index and coeff_value. The first register defines the point of the function, the second the value. Writing to register coeff_value increments the value of coeff_index automatically, so that the next point of the function is addressed. Additionally no register increment will be performed, so that subsequent I2C-bus write addresses always have the same register coeff_value.
If the scaled or non-scaled input frame does not fit into the needed output frame, whether it is to large or to small, the panning unit enlarges the input frame to the size of the output frame. This is achieved by generating a border region around the input frame, or it cuts the input frame down to the size of the output frame. The position of the top left pixel of the input frame inside the output frame must be defined with pic_v_offset and pic_h_offset. The output frame size must be programmed with out_v_size and out_h_size (see Fig.17). If the input frame is to large only the right and bottom part will be cropped. The colour of the generated border region must be set via border_colour_red, border_colour_green, and border_colour_blue.
handbook, full pagewidth
pic_v_offset pic_h_offset pic_v_offset out_v_size pic_h_offset
OUTPUT FRAME INPUT FRAME out_h_size
MHB257
Fig.17 Picture positioning.
1999 May 11
53
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.8 8.8.1 Overlay port OVERLAY INSERTION
SAA6721E
The incoming data from ports ovl0 and ovl1 is replaced by the defined colour information and treated as a double pixel, which will be inserted into the data stream if OVACT is set. The pixel at port 0 is then the left pixel, and the pixel at port 1 is the right pixel. The sampling of the ports ovl0 and ovl1 is done on the positive edge of OVCLK in the event that sample_edge is asserted, otherwise on the falling edge of OVCLK.
If ovl_syncs_active is HIGH, the vertical and horizontal sync signals for the external OSD controller are generated. The flag ovl_insert_active switches on the insertion of the information at the overlay port provided by an external OSD controller into the data stream at the position defined by ovl_v_offset, ovl_hs_start, and ovl_hs_latency (see Fig.18).
handbook, full pagewidth
ovl_hs_latency ovl_hs_start ovl_v_offset ovl_h_length
ovl_v_length ovl_vs_start
OVERLAY WINDOW
one line Vsync
OUTPUT FRAME
MHB258
Fig.18 Overlay window positioning.
1999 May 11
54
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.8.2 SYNC GENERATION 8.8.3 DATA SAMPLING
SAA6721E
The start of the horizontal sync pulse is defined in ovl_hs_start and the polarity in ovl_hs_pol. The sync pulse length is defined in ovl_hs_length (see Fig.19). It is possible to generate a Hsync pulse from one clock cycle length up to longer than the horizontal overlay data. The vertical sync pulse starts at ovl_vs_start and is always one output frame line long.
Data sampling from the two ports OVA and OVB starts from the beginning of the horizontal sync pulse, but the number of clocks defined in ovl_hs_latency will decide when reading data from the overlay port will start (see Fig.19). The end of the sync pulse is not important.
handbook, full pagewidth
ovl_hs_start
ovl_hs_length ovl_hs_latency ovl_h_length
OVCLK
OVHS
OVA
O0
O2
O4
O6
O8
OVB
O1
O3
O5
O7
O9
OVACT
MHB259
Fig.19 Hsync generation and data sampling (Hsync latency = 2).
8.8.4
OVCLK GATING
8.10
Colour correction
All of the above mentioned functions will only work during internal processing of valid video data, and not during internal blanking regions. This can give problems if the overlay window is displayed at the left border of the picture because the first pixels of a line will be processed due to the internal pipeline structure. To overcome this, the OVCLK can be gated to disable data processing by the external OSD controller during internal blanking. Clock gating is enabled by clk_gating_on. 8.9 Colour space matrix
The colour correction unit can be used to perform gamma correction, change of brightness, and so on. This can be achieved by means of a look-up table. Each colour component value in an RGB pixel is used as a pointer into this table. The value from the table will replace the incoming colour. Various tables exist for R, G, and B components. Programming of a table must be performed using the programming registers 47 to 49 (see the colour correction section of the programming register Table 7). It must be decided which component table should be written to (red_prog, green_prog, blue_prog). In colour_index the start address or the first incoming colour value for programming must be written. Then subsequent writing to colour_value fill the table. At this address the I2C-bus address auto-increment stops, but the value programmed into colour_index will be incremented. It is possible to write to more than one table by enabling of programming multiple colour components. 55
The back-end processing of the SAA6721E and the TFT panels require RGB video data. So the built-in colour space matrix is used to convert video data from YUV space into RGB space. It can be enabled by setting csm_bypass to logic 0 (see general configuration section of the programming register Table 7), otherwise the colour space converter will be bypassed.
1999 May 11
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
If the colour correction unit is switched to bypass mode (when colour_correction_on is not asserted), the incoming colours are used for further processing. Writing to the colour correction table is possible during data processing. 8.11 8.11.1 On screen display
handbook, halfpage
SAA6721E
The programming registers osd_v_size and osd_h_size define the OSD window size in characters. The window position inside the output frame must be defined with osd_v_offset and osd_h_offset (see Fig.20).
OSD GENERALS
osd_v_offset osd_h_offset
The implemented OSD is a character based window system. It consists of a character matrix memory where all character definitions are stored, and an OSD window memory defining the OSD window's contents. The OSD window will be inserted into the video data stream if osd_active is set to logic 1. Writing to these memories can be done during data processing. 8.11.2 OSD WINDOW
osd_v_size
OSD OUTPUT FRAME osd_h_size
MHB260
The OSD window contains the character, colour and appearance information to be displayed. Such a definition exists for each character position. A character can use one of 8 different foreground and background colours. Some of these colours can be defined as transparent colours where the original picture information will be displayed instead, as alpha blended colours where a 1 : 1 or 1 : 2 alpha blending will be done between picture and OSD, or as normal colours. Transparency or alpha blending effects will be enabled or disabled for the single characters. The size and outline of the visible OSD window can be programmed as long as the internal memory meets the needs. This memory is able to store information of 1152 characters information.
Fig.20 OSD window positioning.
The OSD can be programmed to use a 24 x 24 character matrix, or a 12 x 16 matrix. The first one should be used for Kanji and the second for standard characters. The selection of the font size is done by char_size. A logic 1 selects 24 x 24 font, and a logic 0 the smaller 12 x 16 font. If the small 12 x 16 font is used, up to 128 different characters can be defined. Alternatively up to 42 characters of the larger 24 x 24 font can be used. Table 18 gives some possible OSD settings.
1999 May 11
56
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
Table 18 OSD window size OSD WINDOW RESOLUTION/PIXELS 24 x 24 32 x 16 40 x 20 48 x 24 768 x 384 960 x 480 1152 x 576 12 x 16 384 x 256 480 x 320 576 x 384 2 The whole OSD window can be zoomed in both directions by a factor of two by setting zoom2 to logic 1. This results in pixel doubling horizontally and vertically. Each character can be displayed using 1 of 8 different foreground and background colours. These sixteen colours can be chosen from the full true colour palette with 8 bits per colour component. The definition of these colours is in registers 144 to 191 (see OSD section of the programming register Table 7). The first 8 colour entries are used for foreground colours, and the second half is used for defining the background colours. Registers 192 to 195 (see Table 7) decide the transparency and alpha blending effects. If one of these effects is enabled for a specific character, only the colours defined as transparency or alpha blending colours will be used to generate these effects. Each character information in the OSD window memory consists of 15 bits of information. This is given in Tables 19 and 20. Table 19 Character appearance definition CHARACTER INFORMATION Character code Appearance Background colour Foreground colour NUMBER OF BITS 7 2 3 3 Table 20 Colour effects APPEARANCE VALUE 0 1
SAA6721E
EFFECT OSD character colours are displayed instead of the picture colours OSD character colours defined as transparency colours will be replaced by the picture colours OSD character colours defined as alpha blending colours will be alpha blended 1 : 1 with the picture colours OSD character colours defined as alpha blending colours will be alpha blended 2 : 1 with the picture colours
OSD SIZE
3
To access a certain character position its coordinates must be programmed into registers 196 (cursor_row) and 197 (cursor_column), see Table 7. After that, the colours and appearance of the character must be defined in address 198 (see Table 7). This definition is valid for all further writes to register 199 (char_code), see Table 7. After writing to this register the cursor position changes to the next right position. At line end it wraps around to the first left character in the line below. I2C-bus auto-increment is not active at register 199 (see Table 7), so that subsequent I2C-bus byte write accesses will define several characters. 8.11.3 OSD CHARACTER MATRIX
Two different font sizes are supported; 24 x 24 and 12 x 16 pixels. With the internal matrix memory 42 characters (24 x 24 pixels) can be defined, or 128 characters (16 x 12 pixels). The definition of the characters is achieved by writing to registers 200 and 201 (see Table 7). The first register must be written to with the character code of the character to be defined. Then the bytes with the pixel pattern must be written to address 201 (see Table 7). The definition of a character is done with 3 bytes per line at 24 x 24 font (72 bytes per character), and with 3 bytes per 2 lines at 12 x 16 font (24 bytes per character), see Fig.21.
The character code is used to address the defined characters inside the matrix memory. The appearance bits decide about transparency and alpha blending, and background and foreground colour are indices to the colour definition registers.
1999 May 11
57
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
The second mode is synchronized to the input data, mainly implemented to support the SAA6721E's no memory mode. In this mode the input data is sent directly to the output interface, which must synchronize its output timing to get the same frame rate as the input. Additionally it starts generating vertical blanking and synchronization signals at pins PVS and PHS directly after releasing the internal reset.
handbook, halfpage
1 byte
(a)
(b)
MHB261
After the programmed top blanking the output interface enlarges the last blanking line until data from the input interface reaches the output interface. Because too long lines cause counter overflows in the panels, a controlling mechanism exists which changes the length of the blanking, border and active lines according to the timing requirements of the panel and the applied graphics mode. This mode can be enabled by setting the programming register sync_mode to logic 1, otherwise the first free running mode will be selected. The length controlling the blanking, border and active video region can be enabled by asserting blank_ctrl, border_ctrl, and active_ctrl. The output interface also supports a Power-down mode which sets all output signals to logic 0. This will be activated by the programming flag power_down (see section general configuration Table 7). For flicker free switching between different input modes, the output interface is able to set all data outputs to the panel to logic 0, resulting in a black picture. Even if during programming and internal reset no synchronization pulses for the panel are generated and the panel loses the last picture information, the panel still displays black colour, because this is its Idle state. To switch the output interface into this mode blank_tft must be set. To enable the panel interface it must be enabled with out_if_enable. The interface supports single pixel (24 bits) and double pixel (48 bits) output in parallel. The selection between these two modes must be done with single_pixel_output. The active clock edge at PCLK can also be selected by clk_pol.
a: 24 x 24 font definition. b: 12 x 16 font definition.
Fig.21 Character matrix organization.
8.12
Temporal dithering (frame rate controller)
The SAA6721E is able to display true colour (8 bits per colour) on high colour displays (6 bits per colour). The algorithm used is temporal dithering. This feature can be enabled by setting frc_on to logic 1 in the general configuration register block (see Table 7). 8.13 8.13.1 Output interface GENERAL
The output interface is the interface between the SAA6721E and the TFT panel. Its timing parameters can be programmed in a wide range to support panels of many different manufacturers. The output interface can operate in two different modes. The first mode is the free running mode which is adapted to the memory mode of the SAA6721E. In this mode the output is independent from the input at the RGB/YUV input interface. So the output frame generation can start directly after releasing the internal reset. For getting a high frame rate the output timing can be programmed to satisfy the minimum timing requirements of the panel.
1999 May 11
58
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.13.2 FRAME GENERATION
SAA6721E
A maximum value must be programmed in h_max_len which is the upper limit for line lengthening during activated control mechanism. In free running mode all 3 counters should be programmed with the same minimum values. If no border is needed, because the active video region covers the visible area of the panel, the active video length counters should point to the same positions as the border length counters. Then the active video length counters have a higher priority. The border colour inserted by the output interface is the same as the blank colour in the memory interface; blank_colour_red, blank_colour_green, blank_colour_blue.
The output frame contains three main regions: * Blanking region * Border region * Active video region. The blanking region contains all front and back porch as well as the synchronization intervals. The border region is visible on the panel and is used for positioning the active video region inside this visible area. To ensure a great flexibility in the `sync to input' mode there are 3 different horizontal length counters (h_len_blank, h_len_border, h_len_active) with independent length control (see Fig.22).
handbook, full pagewidth
h_hs_start
h_hs_end PHS
h_len_border
starting point
v_vs_end v_start
v_active
h_len_blank
active video border PVS v_end blanking
h_de_start
h_active_start
h_de_end
h_len_active
h_max_len
MHB262
Fig.22 Output frame and timing.
1999 May 11
59
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
8.13.3 TIMING REFERENCE SIGNALS
SAA6721E
The position and length of the horizontal synchronization pulses in an output line must be programmed with h_hs_start and h_hs_end. The vertical synchronization pulse starts at line 0 and ends at v_vs_end. The horizontal start offset in line 0 can be set-up with h_vs_start and the horizontal end offset with h_vs_end. The data qualifier PDE frames the display region that should be visible on the panel horizontally. It will be asserted at h_de_start and it will be de-asserted at h_de_end. It frames both horizontal border and active video region.
The SAA6721E supports three timing reference signals to drive the panels: PVS (vertical synchronization pulse), PHS (horizontal synchronization pulse) and PDE (data qualifier). The polarity of these signals is programmable. To program high polarity the three programming registers (vsync_pol, hsync_pol, de_pol) must be set to logic 1. Sometimes panels require that no data qualifier signals must be active during vertical synchronization. The generation of PDE pulses during active PVS can be switched off by de-asserting sync_de_inact.
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all ground pins are connected together and all supply pins are connected together. SYMBOL VDDD VDD(PLL) Vn VSS Tstg Tamb Tamb(bias) Ves Note 1. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k resistor. PARAMETER digital supply voltage PLL supply voltage voltage at digital inputs and outputs voltage at digital output voltage difference between VSS(PLL) and VSS(D) storage temperature ambient temperature operating bias ambient temperature electrostatic handling voltage for all pins note 1 outputs active CONDITIONS MIN. -0.5 -0.5 outputs in 3-state -0.5 -0.5 - -65 0 -10 -2 MAX. +4.6 +4.6 +5.5 100 +150 70 +70 +2 V V V mV C C C kV UNIT
VDDD + 0.5 V
1999 May 11
60
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
10 CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDD(PLL) = 3.1 to 3.5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VDDD IDDD PD VDD(PLL) IDD(PLL) PPLL PPLL + D digital supply voltage digital supply current digital power dissipation PLL supply voltage PLL supply current PLL power dissipation digital plus PLL power dissipation 3.0 - - 3.1 - - - 3.3 600 2 3.3 tbf tbf 2 3.6 tbf - 3.5 tbf - - PARAMETER CONDITIONS MIN. TYP.
SAA6721E
MAX.
UNIT
V mA W V mA W W
Digital inputs VIL(SCL, SDA) LOW-level input voltage at pins SDA and SCL VIH(SCL, SDA) HIGH-level input voltage at pins SDA and SCL VIL(LVTTL) VIH(LVTTL) ILI Ci LOW-level input voltage at LVTTL pins HIGH-level input voltage at LVTTL pins input leakage current input capacitance input capacitance at all other inputs Digital outputs VOL(SDA) VOL(CMOS) VOH(CMOS) VOL(LVTTL) VOH(LVTTL) LOW-level output voltage SDA at 3 mA sink current - at pin SDA SDA at 6 mA sink current - LOW-level output voltage at CMOS pins HIGH-level output voltage at CMOS pins LOW-level output voltage at LVTTL pins HIGH-level output voltage at LVTTL pins - 2.4 - 0.85VDDD - - - - - - 0.4 0.6 0.4 - 0.4 - V V V V V V outputs at 3-state -0.5 0.7VDDD -0.5 2.0 - - - - - - - - - - +0.3VDDD V
VDDD + 0.5 V +0.8 V
VDDD + 0.5 V 10 8 5 A pF pF
1999 May 11
61
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
11 TIMING CHARACTERISTICS VDDD = 3.0 to 3.6 V; VDD(PLL) = 3.1 to 3.5 V; Tamb = 25 C; see Fig.23; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. - 50 - - 50 TYP.
SAA6721E
MAX.
UNIT
System clock input at pin CLK fCLK clock frequency duty factor 24 40 70 60 MHz %
RGB/YUV sample clock input at pin VCLK fVCLK clock frequency duty factor single ADC mode double ADC mode 25 12.5 40 150 75 60 MHz MHz %
Input signals at pins VVS, VHS, VPA7 to VPA0, VPB7 to VPB0, VPC7 to VPC0, VPD7 to VPD0, VPE7 to VPE0, and VPF7 to VPF0 with respect to signal at pin VCLK tsu th th tPD fPCLK set-up time hold time -4.0 7.0 - - - - - 50 - - - 13 ns ns
Output signals at pins CLAMP and GAINC with respect to signal at pin VCLK; note 1 hold time propagation delay 8 - - 40 ns ns
Output clock to panel at pin PCLK clock frequency duty factor 80 60 MHz %
Output signals at pins PVS, PHS, PDE, PAR7 to PAR0, PAG7 to PAG0, PAB7 to PAB0, PBR7 to PBR0, PBG7 to PBG0, and PBB7 to PBB0 with respect to signal at pin PCLK; note 2 th hold time pins PVS, PHS and PDE all other pins tPD propagation delay pins PVS, PHS and PDE all other pins Overlay port clock output at pin OVCLK fOVCLK clock frequency duty factor 40 50 - - - - 80 60 - - - 1.0 MHz % - - - - 1 3.5 ns ns -0.5 0 - - - - ns ns
Input signals at pins OVACT, OVA2 to OVA0, and OVB2 to OVB0 with respect to signal at pin OVCLK tsu(i) th(i) th(o) tPD(o) set-up time hold time 6.0 -3.0 -1.0 - ns ns
Output signals at pins OVVS and OVHS with respect to signal at pin OVCLK; note 1 hold time propagation delay ns ns
1999 May 11
62
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
SYMBOL
PARAMETER
CONDITIONS - -
MIN. - -
TYP.
MAX.
UNIT
Memory port clock output; pin MCLKO fMCLKO CL frequency load capacitance duty factor 125 20 60 MHz pF %
40 - 40 6.5
50 - 50
Input signal at pin MCLKI with respect to signal at pin MCLKO; see Fig.24 fMCLKI tPD tsu th frequency duty factor propagation delay 125 60 10 - - - - MHz % ns
Input signals at pins DQ63 to DQ0 with respect to the negative edge of signal at pin MCLKO set-up time hold time 6.0 -3.0 ns ns
Output signals at pins DQ63 to DQ0, RAS, CAS, WE, A10 to A0, and BA with respect to the negative edge of signal at pin MCLKO; note 3 th hold time pins DQ63 to DQ0 pins RAS, CAS, WE, A10 to A0, and BA tPD propagation delay pins DQ63 to DQ0 pins RAS, CAS, WE, A10 to A0, and BA Notes 1. CL = 15pF, Io = 2 mA and RL = 2 k. 2. CL = 15pF, Io = 4 mA and RL = 2 k. 3. CL = 10pF, Io = 4 mA and RL = 2 k. - - - - 1.0 1.0 ns ns -1 0 - - - - ns ns
1999 May 11
63
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
SAA6721E
handbook, full pagewidth
clock input
1.5 V
data input tsu(i) th(i) data output data valid th(o) tPD(o) data transition period
MHB490
tsu(i): input set-up time; data input must be stable before active clock edge. th(i): input hold time; data input must be stable after active clock edge. tPD(o): output propagation delay; output data becomes stable with respect to active clock edge. th(o): output hold time; output data stays stable with respect to active clock edge.
Fig.23 Data timing diagram.
handbook, full pagewidth
MCLKI
1.5 V
MCLKO
tPD
MHB491
Fig.24 Memory clock timing.
1999 May 11
64
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
12 APPLICATION INFORMATION
SAA6721E
handbook, full pagewidth
VIDEO PORT
SAA7113A
YUV
SDRAM 16 MBits
SDRAM 16 MBits
SDRAM 16 MBits
SDRAM 16 MBits
EEPROM RGB
TDA8752
VGA PORT
SAA6721E MICROCONTROLLER P87C695 TDA8752 RGB I2C-bus
PANEL PORT
USB
MHB263
Fig.25 Test board.
1999 May 11
65
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
13 PACKAGE OUTLINE BGA292: plastic ball grid array package; 292 balls; body 27 x 27 x 1.75 mm
D D1
SAA6721E
SOT489-1
ball A1 corner A2 E1 E detail X A1 A
k
k e
Y W V U T R P N M L K J H G F E D C B A 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ZD b
w M
A vA ZE y
e
20
X 10 scale 20 mm
0
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.46 A1 0.70 0.50 A2 1.85 1.62 b 0.90 0.60 D 27.2 26.8 D1 24.7 24.0 E 27.2 26.8 E1 24.7 24.0 e 1.27 k 4.0 3.9 v 0.35 w 0.3 y 0.15 ZD 1.84 1.04 ZE 1.84 1.04
OUTLINE VERSION SOT489-1
REFERENCES IEC JEDEC EIAJ
EUROPEAN PROJECTION
ISSUE DATE 98-05-06
1999 May 11
66
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
14 SOLDERING 14.1 Introduction to soldering surface mount packages
SAA6721E
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 May 11
67
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
14.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP HLQFP, HSQFP, HSOP, SMS PLCC(3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable
SAA6721E
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 May 11
68
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA6721E
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale 17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 May 11
69
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
NOTES
SAA6721E
1999 May 11
70
Philips Semiconductors
Preliminary specification
SXGA RGB to TFT graphics engine
NOTES
SAA6721E
1999 May 11
71
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA 64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/750/01/pp72
Date of release: 1999 May 11
Document order number:
9397 750 04392

▲Up To Search▲

Price & Availability of SAA6721

	To Download SAA6721 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .